As part of the international collaboration between Fermilab and the Institute for High Energy Physics (IHEP), Beijing, a silicon strip detector was built to augment the instrumentation at the IHEP test beam facility. Information on particle trajectories at the IHEP test beam was obtained with wire chambers with limited resolution. To improve on the position resolution a 5-layer silicon strip detector was designed and built as a collaborative effort between Fermilab and IHEP. The detector employs silicon strip detectors with 10cm long strips with a pitch of 60 microns covering an active area of 12cm x 10cm.
The telescope system consists of two stations. The first station has three layers of strip detectors at an orientation of +/-5.7 and 90-degrees. The second station, 5cm downstream, consists of two layers of strip detectors with an orientation of 90 +/- 5.7 degrees. The five layers of silicon detectors are arranged to form a small beam telescope. Each layer employs three 639-channel silicon strip detectors left over from the DZero experiment at Fermilab, totaling 1917 silicon strips per layer. The strips are read out via wire-bond connections to VA1’ ASICs (mounted on Hybrid printed circuit boards), which are 128-channel sample and hold chips that simultaneously store the charge from the channels when beam arrives, and hold each channel’s charge for later readout. Readout occurs by applying a 3.9 MHz bipolar clock, with clock edges driving the channel differential current on the output pins. There are five VA1’ chips residing on each of three Hybrid Boards, which are mounted on a common frame with the detectors. The Hybrids also carry support components for the ASICs, including power supply bypassing, current sourcing for the preamplifiers and shapers, voltage biasing for the preamplifiers and shapers, and a temperature monitoring IC. The Hybrids are connected to the Adapter Card via 12cm long custom copper-over-kapton flexible circuits. The Adapter Card supplies +2V and -2V power to the ASICs, buffers the control signals from LVTTL to the +1.8V/1.8V logic levels required by the ASICs, and translates the differential current output of the ASIC’s analog output into the differential voltage which is input to a multichannel ADC. The ADC resides on a CAPTAN data acquisition node (reference 1) directly connected to the Adapter Card. Five CAPTAN nodes are used to support the telescope and deliver readout data to the analysis computer via independent gigabit Ethernet links. The system software includes a GUI to configure the CAPTAN nodes as well as analysis and diagnostic tools to characterize the performance of the detector components. The CAPTAN node forms the control signals needed by the ASICs, digitizes and stores the analog data coming from the ASICs, and interfaces to the temperature readout IC on the Hybrid. All boards are designed by Fermilab for low noise and simplicity of connection.
The performance of the system will be described and some unanticipated features and their remedies will be highlighted.
 CAPTAN: A Hardware Architecture for Integrated Data Acquisition, Control, and Analysis for Detector Development, N70-3, IEEE Nuclear Science Symposium, 2008.