PLENARY 4 - New interconnect technologies
- Jorgen Christiansen (CERN)
Piet de Moor (IMEC)
9/22/10, 2:15 PM
Although CMOS technology has a proven track record in terms of performance, there are limitations of a single chip (and even more of a full system containing many chips) in terms of the traditionally lateral interconnects. The past years a lot of R&D was spent to develop 3D interconnect and integration technologies such as high density bump interconnects, through Si vias and advanced...