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TWEPP 2010 Topical Workshop on Electronics for Particle Physics

20–24 Sept 2010
Aachen, Germany
Europe/Zurich timezone

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Session

Programmable Logic, design tools and methods

23 Sept 2010, 09:50
Aachen, Germany

Aachen, Germany

RWTH Aachen University Templergraben 55 52056 Aachen

Conveners

Programmable Logic, design tools and methods: Parallel Session B5a

  • Magnus Hansen (CERN)

Programmable Logic, design tools and methods: Parallel Session B5a

  • Magnus Hansen (CERN)

Presentation materials

There are no materials yet.

  1. 46. Digitization and real-time analysis of detector signals with GANDALF
    Louis Lauser (Physikalisches Institut, Albert-Ludwigs-Universität Freiburg)
    23/09/2010, 09:50
    Programmable Logic, design tools and methods
    Oral
    The Recoil-Proton Detector at COMPASS is built to identify protons of DVCS-processes and to trigger on the recoil particle. A front-end module was designed that allows both precise digitization of photomultiplier signals and real-time data-processing. With GANDALF, signals of 16 channels are converted by 12-bit 500 MHz ADCs, zero-time approximation is accomplished by DSP-algorithms in a...
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  2. 49. The IBL Readout System
    Mr Jens Dopke (University of Wuppertal)
    23/09/2010, 10:15
    Programmable Logic, design tools and methods
    Oral
    With higher instantaneous luminosity, the present Pixel detector system will run into readout inefficiencies. To compensate for those and yet provide good impact parameter resolution with an upgraded LHC, a Layer designed for reading out higher occupancies is to be inserted into Pixel during the Phase1 Upgrade of ATLAS. This additional layer, called IBL (Insertable B-Layer), will include newly...
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  3. 51. A readout driver for the ATLAS LAr calorimeter at super-LHC
    Steffen Staerz (Inst. fuer Kern- und Teilchenphysik (IKTP)-Technische Universita)
    23/09/2010, 11:00
    Programmable Logic, design tools and methods
    Oral
    A new readout driver (ROD) is being developed as a central part of the signal processing of the ATLAS liquid-argon calorimeters for operation at the sLHC. In the architecture of the upgraded readout system, the ROD modules will have several challenging tasks: receiving of up to 1.4 Tb/s of data per board from the detector front-end on multiple high-speed serial links, low-latency data...
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  4. 61. Optimizing latency in Xilinx FPGA implementations of the GBT
    Steffen Lothar Muschter (Stockholm University)
    23/09/2010, 11:25
    Programmable Logic, design tools and methods
    Oral
    The GigaBit Transceiver (GBT) has been developed to provide data transmission and to replace the Timing , Trigger and Control (TTC) system between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, has been released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation. This code...
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