PRR of the NSW Trigger Processor Part 2

Session

Trigger Processor Firmware

6 May 2020, 14:20

Vidyo Only (CERN)

Description

including corresponding validation/tests using carrier v2/mezzanine v2

Presentation materials

Firmware Requirements & implementation V2.1

NSWTP_FW_Requirements_Implementation_V2.0.pdf

8. Micromegas: L1A and readout (thru carrier). Algorithms and time alignment.

Nathan Felt (Harvard University (US)), Nathan Felt (Unknown), Thiago Costa De Paiva (University of Massachusetts (US))

06/05/2020, 14:25

11. sTGC stage-0: L1A and readout (thru carrier). Stage-0 algorithm; time alignment

Enrique Kajomovitz Must (Department of Physics), Enrique Kajomovitz Must (Technion, Israel Institute of Technology)

06/05/2020, 14:55

12. Merge block, and output formatter to SL.

George Chatzianastasiou (University of Innsbruck (AT))

06/05/2020, 15:25

7. Results of combined tests with SL. Fixed latency. Latency measurements.

Lorne Levinson (Weizmann Institute of Science (IL))

06/05/2020, 15:55