Conveners
Project Reports II
- Marc Dobson (CERN)
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Aoto Tanaka (University of Tokyo (JP))09/06/2021, 13:30
In the phase-2 front-end system of the ATLAS Thin-Gap Chambers (TGC), a System-on-Chip(SoC)-based control module (JATHub) will take responsibility for the service and calibration around the frontend processing board (PS-board): (1) Configuration and soft error mitigation of the PS-Board FPGA, and (2) the clock phase monitoring, measurements, and alignment for high-performance hit BC assignment...
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John David Hobbs (Stony Brook University (US)), Robert Dean Schamberger Jr (Stony Brook University (US))09/06/2021, 14:00
The Smart Rear-Transition Module (SRTM) of the ATLAS Liquid Argon Calorimeter off-detector electronics has a Zynq Ultrascale+ device as its main processing component. First version boards have arrived and been successfully tested. We will introduce the board, discuss the software and firmware used in the testing as well as the petalinux and development process we've used. Finally, we include...
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Hamza Boukabache (CERN), Juha Hast (European Spallation Source)09/06/2021, 14:30
CROME is CERN new RadiatiOn Monitoring Electronics. The system will homogenize both the radiation protection and environmental monitoring by end of LS3. Currently installed at the PSB, PS, SPS, SM18 and the North Area at CERN, CROME system encompasses a new generation of radiation detectors, alarm units, uninterruptible power supplies and interlock signal aggregators.
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Most of our equipment... -
Dan Gastler (Boston University (US))09/06/2021, 15:15
I will be giving an update on the Apollo platform service module's second HW revision.
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This revision works with both 7 and US+ series of Enclustra SoCs and I will be covering our experiences moving to US+.
Additionally I will show updates to our use of uHAL address tables to build and access AXI IP and HDL devices and how they are integrated into Linux and accessed via UIOuHAL. -
Luis Ardila (KIT-IPE)09/06/2021, 15:45
In the context of the CMS Phase-2 tracker back-end processing system, two mezzanines based on the Zynq Ultrascale+ Multi-Processor System-on-Chip (MPSoC) device have been developed to serve as centralized slow control and board management solution for the Serenity-family ATCA blades.
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The Serenity family consists of two ATCA-sized boards designed to explore alternative configurations.... -
Nick Karcher (Karlsruhe Institute of Technology (KIT)), Oliver Sander (KIT - Karlsruhe Institute of Technology (DE))09/06/2021, 16:15
We utilize MPSoC/RFSoC devices for various applications, including slow control for the CMS experiment (MPSoC), readout of superconducting sensors (MPSoC), and control of quantum bits (RFSoC). The major advantage of MPSoC architectures is the feasibility of flexible and custom hardware-software partitioning. This flexibility comes for the price of additional system complexity. In this...
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Jesra Tikalsky (University of Wisconsin Madison (US)), Thomas Andrew Gorski (University of Wisconsin Madison (US))09/06/2021, 17:00
Our talk will cover various aspects of Embedded Linux on SoC devices in the APx environment. The APx environment is a family of FPGA cards in the ATCA form factor, for trigger processing and DAQ readout in the CMS detector. The Embedded Linux environment operates on a Xilinx ZYNQ SoC-based mezzanine called the ELM# (currently a ZYNQ-7000 based ELM1 and a ZYNQ UltraScale+ based ELM2 exist)....
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Ralf Spiwoks (CERN)09/06/2021, 17:30
The Muon to Central Trigger Processor Interface (MUCTPI) of the first-level trigger of the ATLAS experiment was upgraded for the next run of the Large Hadron Collider (LHC) at CERN. It uses a Xilinx Zynq System-on-Chip (SoC) for configuration, control, and monitoring of the hardware and the operation of the MUCTPI. We present how Gitlab continuous integration can be used for building all the...
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Petr Zejdl (CERN)09/06/2021, 18:00
A proposal for the system software design for ZYNQ MPSoC based hardware running in ATCA crates will be presented, as well as it's implementation. The proposed design takes into account specificities of the ZYNQ embedded systems and the CMS network environment. These specificities include system configuration, network configuration, network boot of systems, as well as specificities of the ATCA...
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Andre David Tinoco Mendes (CERN)09/06/2021, 18:30