2nd System-on-Chip Workshop - CERN

7 Jun 2021, 13:00 → 11 Jun 2021, 18:30 Europe/Zurich

Zoom

Diana Scannicchio (University of California Irvine (US)), Frans Meijers (CERN), Marc Dobson (CERN), Ralf Spiwoks (CERN), Revital Kopeliansky (Indiana University (US))

This is the 2nd CERN SoC workshop, a follow-up from the 1st workshop held in June 2019.

The aim of the workshop is to report on progress of the various SoC projects and of the common tools and solutions available.

The workshop is virtual and all the presentations will take in the Zoom "SoC Workshop - Plenary", see below.
For live informal discussions a Mattermost channel has been set up.

In addition, the "SoC Workshop - Ad-hoc Discussion" rooms 1-4 are available for ad-hoc discussions.

Monday 7 June

13:00 → 13:15 Welcome

Convener: SoC Workshop Organisers

Video of Introduction and some vendor presentations

13:00 Introduction

Speaker: Ralf Spiwoks (CERN)

SoCWS_Spiwoks_INTRO_20210607.pdf

SoCWS_Spiwoks_INTRO_20210607.pptx

13:15 → 18:15 Vendor Presentations

Convener: Revital Kopeliansky (Indiana University (US))

SoCWS_Minutes_Vendors.pdf

Video of MicroChip presentation

Video of Trenz and Enclustra presentations, as well as general discussion

Video of Xilinx presentation (also contains the Introduction)

13:15 Xilinx

XILINX, leading provider of all-programmable logic devices, pursues its strategy for embedded
processors: soft processors like MicroBlaze or ARM Cortex-Mx when a microcontroller is needed,
and hard processors for higher performance applications.
Starting with PowerPC nearly 20 years ago, XILINX offers coherent embedded processing solutions from the
Zynq-7000 SoC (ARM Cortex-A9), Zynq US+ MPSoC (ARM Cortex-A53) and to the latest Versal ACAP
(Adaptive Compute Acceleration Platform with ARM Cortex-A72 processors).
This technical presentation gives a short overview of the latest exciting updates from XILINX: How does
XILINX expands its scalable portfolio with smaller Zynq US+ MPSoC’s ? How does integration in SoC’s go
further with high end Analog converters inside Zynq US+ RFSoC platforms? How is 7nm Versal ACAP more
than a SoC, designed for heterogeneous acceleration?
This session also aims at showing how XILINX wants to provide a new path to “Whole Application
Acceleration”, for any HW or SW engineer, with the KRIA K26 System On Module (SoM) and the ALVEO U30
Acceleration Card.

Speakers: Mr Gregory Donzel (Avnet Silica), Mr Marco Hoefle (Avnet Silica), Mrs Monique Ruch Cavin (Avnet Silica )

CERN - XILINX SoC_SoM_Slides.pdf

Power consumption

14:10 Intel/Altera

To begin with, this presentation will provide introductory details about Intel SoC FPGA product offerings, from
the latest 10nm Agilex SoCs to 28nm Cyclone V SoCs.
The Intel Agilex & Stratix 10 SoC FPGAs features the Quad core Arm Cortex A53 processor and the
Arria10/CycloneV SoC FPGAs features the dual core cortex A9 processors.
We will briefly go through the evolution of family members and their technical differences.
Required Intel software tools/infrastructure to build, integrate and debug the Intel FPGA SoCs will be
discussed, along with the required cross compilers and the host requirements.
Then we will cover the latest Secure Device Manager (SDM) features in Agilex together with the configuration
options.
The presentation will move on to discuss Remote System Update feature, which allows a secure way to update
the devices in field.

Speaker: Mr Sunil Kallur Ramegowda (Intel Corporation)

Intel_SoC_CERN2021_SunilKR.pdf

15:05 Microchip

Flash-based FPGA’s/SoC’s offer key differentiators for the electronics designers. Since 1985, ACTEL had been
serving markets for which power, safety, security and longevity are critical parameters. Acquired in 2010 by
MICROSEMI, it is now MICROCHIP since 2018. First FPGA company to embed hardened Cortex-Mx ARM
processors in their FPGA’s ten years ago, MICROCHIP innovates today with the PolarFire SoC.
The PolarFire SoC takes the best from the hardware features of the PolarFire FPGA, and enables Linux and
real-time applications, with hardened and open ISA platform RISC-V processors. This short presentation aims
at giving an overview of this new and unique SoC family. It also gives an opportunity to show how to start with
the PolarFire SoC devices and their associated tools.

Speakers: Mr Gregory Donzel (Avnet Silica), Mrs Monique Ruch Cavin (Avnet Silica)

CERN - MICROCHIP PolarFire SoC - Slides.pdf

15:35 Coffee/tea break

15:45 Trenz

Using System-on-Modules (SoMs) has clear benefits, e.g. reduced development time and cost, upgradability, use
of widely tested designs and many more, but there are also drawbacks and pitfalls which have to be taken into
account during integration.
This talk will depict the advantages of different SoM series based on the Trenz Electronic product portfolio;
give hints for the choice of suitable SoMs for specific application from low-cost to high-end; show how
disadvantages can be overcome by variation and customization; give a deeper insight into the SoM specific
hardware; discuss which issues have to be addressed during integration and how Trenz Electronic is going to
support and assist you during this process (free of charge). Furthermore we will give an introduction to our
online available documentation, reference designs and demos, the corresponding software tools and how to
use this for effective system development.
Summed up, the talk presents a comprehensive guide from product selection to successful hardware integration
of Trenz Electronic products into a customer System.

Speaker: Mr Martin Rohrmüller (Trenz Electronic GmbH)

20210607_Trenz_CERN_presentation.pdf

16:40 Enclustra

FPGA-based System on Modules (SOM) combine all relevant parts to build an embedded system. They help
reducing development time and risk as well as total cost of ownership by a significant amount. SOMs offer many
advantages over chip-down designs. The high production quantity of off-the-shelf modules reduces their cost
and at the same time provide a proven and reliable solution with a large ecosystem. Enclustra develops and
sells its own off-the-shelf FPGA/SoC modules and IP Solutions and offers development services to customers –
since more than 15 years ago.
This presentation gives an overview of the large SOM product portfolio of Enclustra with more than 20 SOM
series and over 70 models. With three different product families, modules based on devices from Xilinx (Zynq
& Zynq UltraScale+ MPSoC), Intel (Cyclone V SoC & Arria 10 SoC) and soon Microchip (PolarFire
SoC), an Enclustra SOM for almost all applications is available.
Equally important as the module is the ecosystem to speed up the design-in of the module into the application.
The second part of the talk focuses on tools and support to get the job done. Amongst others, the following
topics are covered: Reference Designs, Board Support Packages (BSP/Linux) and debugging options. Application Notes, footprints, user schematics,
pinouts in Excel, IO net length, MTBF reports, 3D models and heat sink solutions.

Speakers: Mr Aimad Rhatay (Enclustra), Mrs Diana Ungureanu (Enclustra)

EnclustraCERNPresentation.pdf

products

Tuesday 8 June

13:30 → 15:15 Overview Presentations

Convener: Ralf Spiwoks (CERN)

SoCWS_Minutes_Overview.pdf

Video of the overview presentations

13:30 ATLAS Overview

Overview of the SoC usage in ATLAS, challenges and coordination of related solutions.

Speaker: Revital Kopeliansky (Indiana University (US))

ATLASSoCRequirements.pdf

ATLAS_SoC_review_SoC_WS_June2021.pdf

13:55 CMS Overview

Overview of the CMS DAQ system and the Phase-2 upgrade. Summary of the use of SoC.

Speaker: Frans Meijers (CERN)

FM-20210608-soc2021-cmsdaq.pdf

14:20 Overview of SoC-related Activities in the Accelerators&Technology Sector

High-level overview of projects based on System-on-Chip, associated developments and future strategy in the Accelerator and Technology Sector.

Speaker: Mamta Ramendra Shukla (CERN)

SoC Overview A&T.pdf

15:00 Coffee/tea break

15:15 → 19:00 Project Reports I

Convener: Ralf Spiwoks (CERN)

SoCWS_Minutes_Projects1.pdf

Video of the SoCs for DCS and Pixel RCE presentations

Video of the TREX, Tile DCS and gFEX presentations

Video of the Wafeform Digitizing presentation by Nalu Scientific LLC

15:15 SoC-based Monitoring and Configuration of the ATLAS L1Calo TREX Module

As part of the ATLAS Level-1 Calorimeter trigger (L1Calo) Phase-I upgrade, the Preprocessor system is being extended with new Tile Rear Extension (TREX) modules.
For every bunch-crossing, the TREX provides digitized energy data from the Tile hadronic calorimeter to the new L1Calo feature extractor processors via high-speed optical links at 11.2 Gbps.
The TREX is equipped with a Kintex Ultrascale and 4 Artix-7 FPGAs, as well as with a Zynq Ultrascale+ MPSoC. The slow-control monitoring is carried out on the processing system (PS) running a CentOS 7 based operating system with an OPC UA server. The programmable logic (PL) is used to configure the on-board devices and FPGAs as well as an interface to VME. The Zynq MPSoC acts as a JTAG master for configuring the FPGAs and the SPI flash memories.
This contribution presents the functionality and the design choices of the SoCs on the TREX boards and the module operation in ATLAS.

Speaker: Tigran Mkrtchyan (Ruprecht Karls Universitaet Heidelberg (DE))

TREX_SoCWJune.pdf

15:45 SoC Developments for the Detector Control System of ATLAS Tile Calorimeter at the HL-LHC

The Tile Calorimeter (TileCal) is part of the ATLAS detector and is the central hadronic calorimeter. The Tile PreProcessor (TilePPr) is the core of the TileCal off-detector electronics for High luminosity LHC. The TilePPr is composed of several FPGA-based boards to operate and readout the on-detector electronics. As part of the TilePPr module, the Gigabit Ethernet switch (TileGbE) mezzanine board provides network communication to the different submodules, and the Tile Computer on Module (TileCoM) mezzanine is to be used to remotely configure the on-detector electronics and TilePPr FPGAs as well as, to interface the ATLAS DCS system providing monitoring data. This contribution presents the progress on the hardware and software design for the TileCoM as well as integration plans with the TilePPr to remotely control, configure and monitor the Tile Calorimeter Phase-II upgrade. A test bench which includes an Avnet Ultra96-V2 ZYNQ UltraScale+ MPSoC evaluation board and Tile Gigabit Ethernet switch will serve as a basis for the TileCoM mezzanine board as part of the Tile PreProcessor (TilePPr). Two OPC-UA servers will be implemented on the evaluation board to read data and publish it to the clients of the DCS. The first server that is currently implemented will read the Xilinx Analog-to-Digital Converter (XADC) data and, it will be used as a generic project for other ATLAS XADC projects. The second OPC-UA server will also be implemented on the TileCoM which will acquire data from the Compact Processing Module (CPM) through the IPbus and publish the acquired data to the DCS.

Speaker: Mpho Gift Doctor Gololo (University of the Witwatersrand (ZA))

SoC_2021_v2.pdf

16:15 The Zynq MPSoC in the gFEX Hardware Trigger in ATLAS

The Global Feature Extractor (gFEX) is a hardware module that will be installed in the Phase-I Upgrade of the ATLAS experiment to maximise the trigger capabilities and flexibility for selecting events containing large-radius jets, typical of Lorentz-boosted objects. The gFEX makes use of a single module to cover the entire pseudorapidity range of the ATLAS calorimeter. This allows for event-based local pileup suppression and calculation of global quantities such as missing energy. The gFEX board hosts three Vertex Ultrascale+ FPGAs and a Zynq Ultrascale+ SoC used for data management, control, and monitoring of the board. The SoC is loaded with a customized Operating System (OS) built using the Yocto Project with the custom layer meta-l1calo. This talk will discuss the usage and integration of PYNQ software libraries for the gFEX custom hardware, the OPC-UA integration of DCS and the management of IPMC monitoring, and prospective capabilities of the Zynq to run increasingly better classification algorithms utilizing the unique strengths and resources of the SoC layout.

Speaker: Emily Ann Smith (University of Chicago (US))

gFEX SoC Workshop - June 2021.pdf

16:45 Coffee/tea break

17:00 SoCs for Detector Controls and their Applications

SoCs are getting adopted extensively by ATLAS systems for the local control and monitoring of their back-end electronics due to their flexibility towards the hardware through the programmable logic but also the convenience provided for higher level software within the linux platform running on the processing system. OPC UA is the de facto middleware standard for Detector Controls at CERN and quasar framework makes the development of servers using OPC UA easy and efficient, resulting in solutions for a wide and diverse range of SoC-based applications. A common solution for the controls, the Embedded Monitoring Processor (EMP), is a SoM-based device, that is mainly used to interface LpGBT links to the experiments controls network via dedicated quasar servers.
In this contribution, a summary of the SoC projects in ATLAS that foresee the adoption of OPC UA and the latest news on the quasar framework for SoCs will be presented. Finally, the activities around the development of the EMP device and its usage will be highlighted.

Speaker: Paris Moschovakos (CERN)

SoCs for Detector Controls and their Applications.pdf

17:30 SoC-based DAQ for the Pixel Readout Chip RD53a/b

The RCE (Reconfigurable Cluster Element) platform is a general-purpose system-on-chip data acquisition system, varying from a compact standalone bench-top form to ATCA compliant system. It is broadly deployed by several experiments, such as ATLAS, LCLS, LSST, HPS, and ProtoDUNE. We present a new generation bench-top RCE system, including a Xilinx UltraScale+ MPSoC board and a custom FMC adaptor card for the RD53 integrated circuit, which is a pixel readout chip for the Phase II upgrade of ATLAS and CMS. A high-performance RD53a/b chip calibration software is implemented to fit the ARM CPU environment.

Speaker: Zijun Xu (SLAC National Accelerator Laboratory (US))

SoC2021_RCE_SoC_Readout_ZijunXu_Jun8_2021.pdf

18:00 Waveform Digitizing and Processing Front-end Microelectronics for large Experiments

In this talk, we will cover the development of a variety of SoC type high speed waveform digitizers designed with modularity in mind for large experiments. These microchips digitize, readout and process regions of interest of waveforms at 1-12 GSa/s at power and size constraints desired for particle physics applications. The chips are normally divided into 3 sections: analog input stages, mixed signal sampling, storage and digitization stages and a digital stage that performs semi-autonomous control of the mixed signal mechanisms. We will present preliminary results and a path forward to ultimate solutions that will may be interesting for LHC.

Speaker: Isar Mostafanezhad (Nalu Scientific LLC)

2021 Nalu - CERN SoC Workshop Slides.pdf

2021 Nalu - CERN SoC Workshop Slides_rev2.pdf

Wednesday 9 June

13:30 → 19:00 Project Reports II

Convener: Marc Dobson (CERN)

SoCWS_Minutes_Projects2.pdf

Video of the Apollo Platform, Serenity board management mezzanines, and development infrastrcture for MPSoC/RFSoC

Video of the APx Embedded Linux, ATLAS MUCTPI Software Framework, and CMS DAQ System Software Design Considerations

Video of the TGC FE Control System, LAr Smart RTM and SoC Radiation Monitors

13:30 A System-on-Chip-based Front-end Electronics Control System for the Phase-2 ATLAS Thin-Gap Chambers (TGC)

In the phase-2 front-end system of the ATLAS Thin-Gap Chambers (TGC), a System-on-Chip(SoC)-based control module (JATHub) will take responsibility for the service and calibration around the frontend processing board (PS-board): (1) Configuration and soft error mitigation of the PS-Board FPGA, and (2) the clock phase monitoring, measurements, and alignment for high-performance hit BC assignment on PS-Boards. System-level commissioning has been launched at KEK, using prototype boards of JATHub and PS-Board. The functionality of configuration and recovery of the frontend FPGA has been successfully implemented and demonstrated in the test-bench system. The timing calibration methodology for fine-tuning of the clock phase has been developed around the JATHub, which exceeds the required timing resolution for the TGC trigger operation.

Speaker: Aoto Tanaka (University of Tokyo (JP))

aoto-jathub2106SoC_v3.pdf

14:00 The ATLAS Smart Rear-Transition Module of the Liquid Argon Calorimeter

The Smart Rear-Transition Module (SRTM) of the ATLAS Liquid Argon Calorimeter off-detector electronics has a Zynq Ultrascale+ device as its main processing component. First version boards have arrived and been successfully tested. We will introduce the board, discuss the software and firmware used in the testing as well as the petalinux and development process we've used. Finally, we include some open questions and areas where improvements could be made in our system.

Speakers: John David Hobbs (Stony Brook University (US)), Robert Dean Schamberger Jr (Stony Brook University (US))

SOC-SBU-AZ-hobbs-SRTM-20210609.pdf

14:30 Remote Management of SoC-based Radiation Monitors both at CERN and ESS

CROME is CERN new RadiatiOn Monitoring Electronics. The system will homogenize both the radiation protection and environmental monitoring by end of LS3. Currently installed at the PSB, PS, SPS, SM18 and the North Area at CERN, CROME system encompasses a new generation of radiation detectors, alarm units, uninterruptible power supplies and interlock signal aggregators.
Most of our equipment are operated by Zynq SoCs. For the radiation detector, the FPGA part of the SoC collects and processes data from various sensors, executes various algorithms, take decisions every 100ms and transfers the results to the processing system. In parallel, all safety critical measurement are sent by the processing system in real-time to the SCADA supervision using the ROMULUS protocol.
On the other hand, the interlock aggregator's SoC collects interlocking statues provided by 2 fully redundant CPLD and send the information to the CERN control centre using the same protocol.
After giving a general architecture overview of our SoC based equipment, we will focus in this presentation on :
• remote firmware management of 200 operational devices
• on the TCP/IP ROMULUS protocol that we have developed to control our SoCs
• the simulator that we have developed to perform test scale tests
We will conclude with a tangible example (live demo ?) of ESS experience with CROME SoCs integration into EPICS using the ROMULUS protocol.

Speakers: Hamza Boukabache (CERN), Juha Hast (European Spallation Source)

CROME_SoC_Hamza_Boukabache.pdf

SoC_Workshop_REMS_Juha_Hast_2021.pdf

15:00 Coffee/tea break

15:15 Updates on SoC for the Apollo Platform

I will be giving an update on the Apollo platform service module's second HW revision.
This revision works with both 7 and US+ series of Enclustra SoCs and I will be covering our experiences moving to US+.
Additionally I will show updates to our use of uHAL address tables to build and access AXI IP and HDL devices and how they are integrated into Linux and accessed via UIOuHAL.

Speaker: Dan Gastler (Boston University (US))

Dgastler-2021-06-09-ApolloUpdate.pdf

15:45 ZynqMP-based Board Management Mezzanines for the Serenity ATCA Blades

In the context of the CMS Phase-2 tracker back-end processing system, two mezzanines based on the Zynq Ultrascale+ Multi-Processor System-on-Chip (MPSoC) device have been developed to serve as centralized slow control and board management solution for the Serenity-family ATCA blades.
The Serenity family consists of two ATCA-sized boards designed to explore alternative configurations. Serenity-A is designed around a single Virtex US+ FPGA with up to 128 high-speed transceivers and an integrated slow-control and board management MPSoC mezzanine in the "FMC+" format. Serenity-Z contains two sites that utilize Samtec z-ray interposer technology mounting removable FPGA-based daughter cards. The choice of slow-control and board management is flexible between the combination of a Com-EXpress (CMX) Computer-on-Module (CoM), a DIMM-based IPMC, or an integrated MPSoC mezzanine in the "CMX-Extended" format.
In this talk, we present the current revision of both Serenity baseboards and the developments on the MPSoC mezzanines to execute the Intelligent Platform Management Controller (IPMC) software "OpenIPMC" in the real-time processors of the MPSoC. OpenIPMC, upon shelf approval, enables the main power and launches CentOS-based Linux in the application processors of the MPSoC. Furthermore, recent qualification tests of the OpenIPMC software against the PICMG standard will be shown.

Speaker: Luis Ardila (KIT-IPE)

2021-06-09_SoC_Workshop.pdf

16:15 Development Infrastructure for MPSoc/RFSoC Platforms

We utilize MPSoC/RFSoC devices for various applications, including slow control for the CMS experiment (MPSoC), readout of superconducting sensors (MPSoC), and control of quantum bits (RFSoC). The major advantage of MPSoC architectures is the feasibility of flexible and custom hardware-software partitioning. This flexibility comes for the price of additional system complexity. In this contribution, we present our applications and approach to develop SoC firmware for our applications. Based on gRPC, we developed a modular remote procedure call framework that gives flexible network access to the platform. Our Yocto tool flow includes building the FPGA firmware automatically. We also set up an environment that allows unit-testing of firmware modules and a system test framework utilizing MPSoC platforms to test complex hardware/software setups automatically. Integration of other lab devices such as oscilloscopes is possible and allows to include DAC/ADC interfaces in the test. The remote access, in combination with the automatic build and test, made a CI integration possible.

Speakers: Nick Karcher (Karlsruhe Institute of Technology (KIT)), Oliver Sander (KIT - Karlsruhe Institute of Technology (DE))

SoC_SC_Sensors_upload.pdf

16:45 Coffee/tea break

17:00 APx Embedded Linux Developments

Our talk will cover various aspects of Embedded Linux on SoC devices in the APx environment. The APx environment is a family of FPGA cards in the ATCA form factor, for trigger processing and DAQ readout in the CMS detector. The Embedded Linux environment operates on a Xilinx ZYNQ SoC-based mezzanine called the ELM# (currently a ZYNQ-7000 based ELM1 and a ZYNQ UltraScale+ based ELM2 exist). In this talk, we will discuss the APx CentOS framework's current model for management and configuration of our ZYNQ SoCs. This will include a discussion of software deployment, configuration management, geographic IP address assignment, and peripheral identification & mapping. We will outline our current support requirements for both development lab and final production environments, as well as what we would like to see from central IT departments relative to support for embedded linux as an ongoing matter. We will also discuss some limitations we have faced relative to geographic address assignment, and our plans for future work.

Speakers: Jesra Tikalsky (University of Wisconsin Madison (US)), Thomas Andrew Gorski (University of Wisconsin Madison (US))

20210609_APx_Embedded_Linux_Developments.pdf

17:30 Software Framework for the System-on-Chip of the ATLAS MUCTPI

The Muon to Central Trigger Processor Interface (MUCTPI) of the first-level trigger of the ATLAS experiment was upgraded for the next run of the Large Hadron Collider (LHC) at CERN. It uses a Xilinx Zynq System-on-Chip (SoC) for configuration, control, and monitoring of the hardware and the operation of the MUCTPI. We present how Gitlab continuous integration can be used for building all the software needed to operate the SoC, including boot loader, Linux kernel, root file system, Trigger and Data Acquisition software. It also builds the MUCTPI-specific run control applications, which provide the integration of the MUCTPI into the experiment's run control system.

Speaker: Ralf Spiwoks (CERN)

SoCWS_Spiwoks_MUCTPI_20210609.pdf

SoCWS_Spiwoks_MUCTPI_20210609.pptx

18:00 CMS DAQ System Software Design Considerations for Zynq-based MPSoCs in ATCA Crates

A proposal for the system software design for ZYNQ MPSoC based hardware running in ATCA crates will be presented, as well as it's implementation. The proposed design takes into account specificities of the ZYNQ embedded systems and the CMS network environment. These specificities include system configuration, network configuration, network boot of systems, as well as specificities of the ATCA standard such as communication with IPMC, DHCP ClientID based configuration and the system shutdown procedure.

Speaker: Petr Zejdl (CERN)

2021-06-09-SoC_CMS_DAQ_ZYNQ.pdf

18:30 Added Notes: Report on SoC Activities in the CMS HGCAL

Speaker: Andre David Tinoco Mendes (CERN)

SoCWS_AddedNotes_CMS_HGCAL.pdf

Thursday 10 June

14:00 → 17:30 Tutorials

Convener: Ralf Spiwoks (CERN)

Video on Continuous Integration for Building Software Infrastructure

Video on Reliable Booting and Upgrade System

Video on Setting up basic GitLab CI and CD Environment for Zynq-based Designs

14:00 Setting up basic GitLab CI and CD Environment for Zynq-based Designs

This tutorial shows how one can profit from enabling Continuous Integration (CI) and Continuous Deployment (CD) on a Zynq SoC design. The main focus is on automating compilation and deployment of Zynq PL designs using gitlab CI based infrastructure. We start first with basics of setting up firmware development workstation for local development and CI/CD jobs execution. Second, we dive into details of preparing git (gitlab) repository for execution of Vivado compilation flow. A short introduction on automating Petalinux build is also provided. We conclude with showing how to setup an example board for CD i.e. automatic programming directly from gitlab user interface. If time permits a hardware demonstration will be shown (using Pynq-Z2).

Speaker: Michal Husejko (Stanford University (US))

MHusejko-CERN-SoC-2nd-Workshop-2020-JUNE-10r.pdf

15:00 Coffee/tea break

15:15 Reliable Booting and Upgrade System

The complex multi-stage booting process of the Zynq MPSoC introduces possible failures that can prevent the Zynq MPSoC from booting correctly. We have developed a reliable booting system that recovers the Zynq MPSoC from boot failures, upgrade failures, and running failures. In this tutorial, we show how to integrate the Reliable Booting and Upgrade mechanisms into your own Zynq Ultrascale+ MPSoC project. The tutorial consists of PetaLinux recipe modifications, and Reliable Booting and Upgrade Linux service installation and configuration. Finally, we test the Reliable Booting system by introducing some failure scenarios, and we will see how the mechanisms can recover the Zynq MPSoC and bring it to a well-known state.The upgrade of the CMS DAQ system involves the installation of new electronics that will also host the Zynq Ultrascale+ MPSoC from Xilinx (Multiprocessor Systems on a Chip). The Zynq Ultrascale+ MPSoC will run control and monitoring software on a Linux operating system (OS).

Speaker: Nekija Dzemaili (Rice University (US))

10-06-2021 RelBoot and RelUpgrades for Zynq US+ MPSoC.pdf

16:15 Coffee/tea break

16:30 Continuous Integration for Building Software Infrastructure

This tutorial gives an introduction on how to automatize the process of building all the software components required for running an SoC (bootloader, kernel, root file system, user software). It gives a tutorial on how to use Gitlab CI and Docker for cross compilation. It shows all the steps necessary for setting up a complete pipeline, from configuring Gitlab runners and creating Docker images through building petalinux and configuring a root file system up to building of the user software using CMake. Everything is shown as a practical example based on a ZCU102 board.

Speaker: Maciej Wyzlinski (AGH University of Science and Technology (PL))

support_materials.pdf

Friday 11 June

14:00 → 17:30 Common Issues

Convener: Wainer Vandelli (CERN)

SoCWS_Minutes_Common.pdf

Video of ATLAS TDAQ Online Software Plans for SoC, and CentOS Stream 8 and ARM64 Linux Support

Video on System and Network Administration, IT Security presentations and the overall discussion

14:00 ATLAS TDAQ Online Software Plans for SoC

We are presenting use cases and high-level functional requirements for a DAQ-to-SoC system communication layer, SoC–DAQ Interface or SoC–DAQI.
It is anticipated that SoCs will play a major role in configuration, control and monitoring of custom ATCA boards of the ATLAS Phase-II subsystems. This implies integration of SoC with TDAQ software infrastructure. The mechanism for this integration is a software layer which allows command and data exchange between SoC and a DAQ application, which is a part of the distributed Run Control tree controlling a data-taking session. A single customized DAQ application serves as a bridge between the DAQ world and a number of subsystem SoCs, using SoC–DAQI library to send commands to applications running on SoCs, process them there and return a result to the DAQ application. In addition to parameters, a command may include arbitrary payload, and the data returned by SoC may also contain a payload.
An implementation of SoC–DAQI is foreseen to be lightweight and on the SoC (server) side to be independent from TDAQ s/w and to rely only on s/w packages available in standard repositories for SoC Operating System, thus not imposing any additional requirements or restrictions on the TDAQ s/w design coming from the SoC architecture.

Speaker: Andrei Kazarov (NRC Kurchatov Institute PNPI (RU))

SoCWorkshop11062021-SoCDAQI.pdf

SoCWorkshop11062021-SoCDAQI.pptx

14:30 CentOS Stream 8 and ARM64 Linux Support

Speaker: Alex Iribarren (CERN)

CentOS Stream 8 and ARM64 Linux Support.pdf

Slides

15:00 Coffee/tea break

15:15 System and Network Administration Aspects of Zynq MPSoC Devices in the Experiments

This presentation will go over the System Administration and networking aspects of the support for Zynq MPSoc embedded controllers in the ATLAS and CMS experiments.
It will cover the ideas about the operating system (OS) for the Zynq, the installation and booting of the OS, the network architecture options and restrictions, the nomenclature proposals for the IP names, and the relations to the functions in the ATCA crate boards, proposal for ClientID usage and information (shelf ID, site type and site number), configuration of ATCA crates (shelf managers), proposals for lab setups, discussion on how to get IPs for the workload FPGA endpoints, etc.
Most information will be common to both ATLAS and CMS, but where there are any differences, this will be shown.

Speaker: Marc Dobson (CERN)

SoC_ATLAS_CMS_SysAdmins_20210611.pdf

SoCWS_Minutes_Sysadmin.pdf

15:45 CERN-IT Security

Speaker: Stefan Lueders (CERN)

SoCWS_Minutes_Security.pdf

Still WTF. About the insecurity of IoT @ CERN (2021).pdf

Still WTF. About the insecurity of IoT @ CERN (2021).pptx

16:15 Discussion

The discussion will be prompted by a couple of polls on technical issues.

We are setting up a list of questions. Please do send us any questions that you would like to be discussed. You can use system-on-chip@cern.ch, the mattermost channel, or bring it up during the discussion.

Speaker: All

Questions_answers_20210611.pdf

17:15 Closure

Speaker: Ralf Spiwoks (CERN)

SoCWS_Spiwoks_CLOSE_20210611.pdf

SoCWS_Spiwoks_CLOSE_20210611.pptx