Speaker
Description
Summary
The FE-Box readout has a modular structure. Four different type of boards are used,
each with its own funcionality, dedicated to a specific stage in the input signal
processing.
At first, charge signals from the straw detector are decoupled from the HV (HV board)
and amplified, shaped and discriminated by the ATLAS ASDBLR chips (ASDBLR board).
Once the signal has been digitized, drift-times are determined and stored in the OTIS
TDC (OTIS board) and sent out to the GOL serializer at
L0 accept (GOL board). Optical fibres carry the data 90 meters far from the detector
to the TELL1 acquisition board at the L0 output rate of 1.1 MHz, in order to be
filtered and finally stored for off-line processing.
The electronics readout requirements is the precise (~0.5 ns) and efficient
drift time measurement at an occupancy of ~4% to ensure single hit resolution (200
micron) and efficient charged particle reconstruction.
To achieve the desired performance, several steps of quality assurance during the
production have been applied, using dedicated test setups for each type of board.
The tested boards have been finally assembled on an alluminium chassis.
The assembled FE-Box is commissioned using a special FE-Tester.
The FE-Tester is based on the test setup build for the Alice Alcapone tester. The
heart of the setup is a PCB with an Altera programmable logic chip. Most of the
electronics needed for the tests is built on the controller board to interface the
FE-Box howewer, a specific connection board is developed (Flipper Box) with the
additional required electronics.
The logic in the Altera is controlled by a LabView program on a PC. The connection
between them is a JTAG interface through the parallel port. For the communication
with the FE-Box the I2C bus is used.
The FE-Tester consist of a programmable pulser with a time resolution of 150 ps
capable to provide all the functionality of the readout (slow and fast controls)
mimicking the real detector.
The following tests have been performed on assembled FE-Boxes:
- Timing. Measurement of the time conversion linearity and the global resolution of
the OTIS board.
-
Threshold Characteristics. A threshold scan is done and the measurement of the
half-efficiency-point is carried out for a fixed input charge.
The relative variation of the half-efficiency-point must be for less than 40 mV all
128 channels as required during the original ASDBLR chip selection.
The test is performed using two test pulse signals (low and high) generated in the
ASDBLR chip. Moreover, an amplitude scan is done and the uniformity the
half-efficiency-point for a fixed threshold is measured. -
Noise. Measurement of the noise is studied as a function of the threshold. In the
threshold range foresee at operation, the noise is required to be less than 40 kHz. -
Synchronization. Four 8 bit TDC are inside a single FE-Box. Tuning the time
difference between test pulse signal and the generated L0, a precision latency scan
is done and therefore the synchronization between channels is verified.
The FE-Setup has been used during the R&D phase of the Outer Tracker electronics. Its
usefullness was proven by finding problems at an early stage and finally it helped to
improve the overall performance. Secondly, the Fe-Tester was used during mass
production of the FE-Boxes, and commissioned each FE-Box before delivery to CERN for
the installation on the Outer Tracker.
