Speaker
Description
Summary
The SLHC is designed to increase the luminosity of the LHC by a factor of ten. In the present ATLAS pixel detector, the electrical signals between the pixel modules and the optical modules (opto-boards) are transmitted via ~ 1 m of micro twisted cable. The optical fiber ribbons consist of 8 m of rad-hard SIMM fibers fusion spliced to 70 m of rad-tolerant GRIN fibers. We currently transmit optical signals at 80 Mb/s and expect to transmit signals at ~ 1 Gb/s at the SLHC. The design of the present pixel optical links has several nice features: 1) Since the optical components are mounted on patch panels instead of directly on the pixel modules, the radiation exposure is much reduced. 2) The separation of the opto-boards from the pixel modules decouples the production of both components and greatly simplifies their design and fabrication. 3) An optical package on a pixel opto-board couples to a removable and robust fiber ribbon terminated with an MT connector. For the SLHC, we would like to take advantage of the many years of R&D effort. If the present architecture can transmit signals at the higher speed, the constraint of requiring no extra service space is automatically satisfied.
We have measured the bandwidths of the transmission lines and the results indicate that the micro twisted-pair cables can transmit signals up to ~ 1 Gb/s and the fusion spliced fiber ribbon can transmit signals up to ~ 2 Gb/s. We have irradiated silicon PIN and GaAs VCSEL arrays with 24 GeV protons and find at least one candidate PIN and one VCSEL array that can survive to the SLHC dosage. We plan to irradiate more silicon and GaAs arrays this sumer. In addition, we plan to irradiate GaAs PIN arrays from three vendors. The results will be presented at the conference.
We previously designed the optical driver and receiver chips using the 0.25 μm process. We are in the process of converting the chips for operation at the much higher bandwidth using the 0.13 μm process. The chips are expected to be submitted for fabrication in a MWP run in the fall. We will present the design of the new chips together with the results from the simulations.
