Sep 26 – 30, 2011
Vienna, Austria
Europe/Zurich timezone

VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter

Sep 29, 2011, 4:00 PM
2h 30m
Vienna, Austria

Vienna, Austria

<font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
Poster Logic Posters

Speaker

Mr Peter Lemmens (KVI, University of Groningen)

Description

Charm-meson resonances and yet undiscovered glueballs might reveal the origin of the hadronic mass spectrum. The PANDA collaboration at the future FAIR synchrotron facility at Darmstadt, Germany, will employ antiproton annihilations to investigate resonances in the charmonium mass region. In order to gain high flexibility for physics event selection, a trigger-less data-acquisition system is employed. A sampling ADC (SADC) readout of the PANDA Electromagnetic Calorimeter (EMC) will allow to realize the desired event-selection approach. The developed feature-extraction algorithm, implemented in VHDL for a commercial 16 bit 100 MHz SADC, and the achieved beam-test results will be discussed during the presentation.

Summary 500 words

The PANDA Electromagnetic Calorimeter (EMC) comprises of the central target calorimeter, read out by large-area avalanche photo diodes (LAAPD), and the forward endcap EMC, read out by vacuum photo triodes (VPT). Cooled PbWO_4 scintillating crystals will be employed for the detection of high-energy photons, electrons and neutral mesons. The gain of the selected photo sensors is not sufficient to directly digitize the output signals. Therefore, special low-power and low-noise preamplifiers were applied, namely the discrete component preamplifier (LNP) for the VPT readout, and the ASIC APFEL for the LAAPD readout. The ASIC has a built-in two-stage shaper and provides two output signals with high and low gains. The LNP is a one-range resistor-reset type with decay constant of 25 micro-s.
For fast and flexible event selection the PANDA experiment will use a trigger-less data acquisition system. Each sub-detector will continuously provide all single-hit event information. Therefore, the EMC-preamplifier signals will be continuously digitized by sampling ADCs (SADC) and the data will be processed on-line in FPGAs. Here we communicate the implementation in VHDL and the achieved test results of a simple, efficient, and robust feature-extraction algorithm, designed to perform the on-line signal-trace processing. Depending on the type of the input signal different processing paths can be selected for the digitized data. For the LNP preamplifier an additional digital pulse shaping can be applied. The raw data from the SADC is processed using the Moving Window Deconvolution filter (MWD). The MWD allows to recover the exponential decay of the LNP signal and produces a step-like function which, after differentiation, results in a semi-rectangular shape of the required length. After the MWD shaping a constant signal-offset is removed by the base-line follower. The base-line subtracted signal is used for triggering and time-stamp determination. The digital implementation of the constant-fraction discrimination (CFD) algorithm is applied to obtain precise timing information. A linear interpolation using two adjacent sampling points is employed for finding the zero-crossing point with a much higher precision than the sampling period. The Moving Average filter (MA) is used to reduce high-frequency noise. Pulse detection is provided by the combined information from the CFD and the MA filters. Once the zero-crossing transition is detected in the CFD signal the output of the MA filter is compared with a threshold. After the identification of the pulse the maximum value of the MA signal is taken as an amplitude measurement. In the signal processing path it is foreseen to use a second MWD filter, which allows to reduce the resulting pulse length in case of input signals with finite rise time. The above described feature-extraction algorithm is used for an unshaped input signal. If analogue shaping is employed, like in the case of the APFEL ASIC preamplifier, both MWD filters of the signal-processing algorithm can be bypassed.
The above outlined feature extraction algorithm and its VHDL implementation, as well as the results and performances obtained in beam-test experiments using an EMC prototype detector will be discussed during the presentation.

Primary authors

Mr Elmaddin Guliyev (KVI, University of Groningen) Mr Ganesh Tambave (KVI, University of Groningen) Prof. Herbert Löhner (KVI, University of Groningen) Dr Myroslav Kavatsyuk (KVI, University of Groningen) Mr Peter Lemmens (KVI, University of Groningen)

Presentation materials