TWEPP 2011 Topical Workshop on Electronics for Particle Physics

Europe/Zurich
Vienna, Austria

Vienna, Austria

<font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
Philippe Farthouat (CERN)
Description

The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.

LHC experiments (and their operational experience) will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.

The purpose of the workshop is :

- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities

- to review the status of electronics for the LHC experiments

- to identify and encourage common efforts for the development of electronics

- to promote information exchange and collaboration in the relevant engineering and physics communities.



Presentations are available here

Proceedings are available here


 

Support
    • 10:00 AM 2:00 PM
      Registration 4h
    • 2:00 PM 3:00 PM
      Welcome Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Philippe Farthouat (CERN)
      • 2:00 PM
        Welcome 1 15m
        Speaker: Philippe Farthouat (CERN)
        Slides
      • 2:15 PM
        Welcome 2 15m
        Speaker: Dr Markus Friedl (Institut fuer Hochenergiephysik (HEPHY)-Oesterreichische Akadem)
        Slides
      • 2:30 PM
        Welcome to the Vienna University of Technology 15m
        Speaker: Jörg Schmiedmayer (Vienna University of Technology)
      • 2:45 PM
        Welcome from Academy of Sciences 15m
        Speaker: Helmut Rauch (Austrian Academy of Sciences)
        Slides
    • 3:00 PM 4:00 PM
      Opening 1 Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Dr Markus Friedl (Institut fuer Hochenergiephysik (HEPHY)-Oesterreichische Akadem)
      • 3:00 PM
        Particle Physics in Austria 30m
        Particle Physics in Austria is diversifying. The accelerator-based experimental efforts are presently being carried out at LHC (ATLAS and CMS) and Belle/ Belle II at KEK. Hadron physics, with emphasis on perturbative QCD studies are being pursued at several research facilities. Recently a major astrophysics and astroparticle physics programme has been launched at Innsbruck. Exciting new particle physics avenues are being explored with precision experiments at ultra-low energies. Theoretical efforts have also been strengthened, particularly in the area of QCD. This vast discovery potential of these various directions is matched with ambitious plans for the further development of the field in Austria.
        Speaker: Christian Fabjan (ÖAW-HEPHY & University of Technology, Vienna)
        Slides
      • 3:30 PM
        Electronics for Particle Physics in Austria 30m
        There are a couple of institutes in Austria dealing with particle physics in various aspects, and most of them also have R&D programs for instrumentation. These institutes belong to universities or the Austrian Academy of Sciences, and the field of research ranges from astroparticle physics to nuclear physics. This presentation will give a brief overview of the institutes and their electronics developments in particular.
        Speaker: Manfred Jeitler (Institut fuer Hochenergiephysik (HEPHY)-Oesterreichische Akadem)
        Paper
        Slides
    • 4:00 PM 4:30 PM
      Coffee Break 30m
    • 4:30 PM 6:00 PM
      Opening 2 Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Philippe Farthouat (CERN)
      • 4:30 PM
        Bio-inspired vision 45m
        Despite all the impressive progress made during the last decades in the fields of information technology, microelectronics and computer science, artificial sensory and information processing systems are still much less effective in dealing with real-world tasks than their biological counterparts. Even small insects still outperform the most powerful computers in routine functions involving e.g. real-time sensory data processing, perception tasks and motor control and are, most strikingly, orders of magnitude more energy-efficient in completing these tasks. The reasons for the superior performance of biological systems are still only partly understood, but it is apparent that the hardware architecture and the style of neural computation are fundamentally different from what is state-of-the-art in artificial synchronous information processing. Very generally speaking, biological neural systems rely on a large number of relatively simple, slow and unreliable processing elements and obtain performance and robustness from a massively parallel principle of operation and a high level of redundancy where the failure of single elements usually does not induce any observable system performance degradation. In the late 1980`s, C. Mead at CalTech demonstrated that silicon VLSI technology can be employed in implementing "neuromorphic" circuits that mimic neural functions and fabricating building blocks that work like their biological role models i.e. neurons, axons, ganglions, photoreceptors etc. Neuromorphic systems, as the biological systems they model, are adaptive, fault-tolerant and scalable, and process information using energy-efficient, asynchronous, event-driven methods. The greatest success of neuromorphic systems to date has been in the emulation of sensory signal acquisition and transduction, most notably in vision. This talk discusses the motivation for looking at nature as a source of inspiration for constructing the next generation of information processing systems and argues that the application of biological computational principles has the potential to overcome technological and architectural limitations faced by modern VLSI-based digital computers. Recent developments in biomimetic vision, one of the most successful fields of neuromorphic engineering, are presented and possible future directions for computer vision are suggested.
        Speaker: Dr Christoph Posch (Austrian Institute of Technology GmbH)
        Paper
        Slides
      • 5:15 PM
        Semiconductor Manufacturing in Austria 45m
        Austriamicrosystems as a globally acting, specialty semiconductor manufacturer with headquarters in Unterpremstätten, Austria, is a nucleation point for a lot of leading edge research in the semiconductor field. With its foundry services and “all-under-one-roof” offers, the company has a long history in providing open access to specialty analog semiconductor processes for the past 3 decades. The presentation is showcasing the companies capabilities, services and contributions to the scientific community, and gives an outlook to future new technologies under development.
        Speaker: Dr Rainer Minixhofer (Austriamicrosystems AG)
        Slides
    • 6:00 PM 6:45 PM
      Art & History of Vienna Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Dr Markus Friedl (Institut fuer Hochenergiephysik (HEPHY)-Oesterreichische Akadem)
      • 6:00 PM
        Art & history of Vienna 45m
        The city of Vienna was essentially founded by the ancient Romans. In the late middle ages, it became the capital of the Habsburg Empire, and consequently grew in size and importance. Even though there are some Roman excavations, most of the architectural heritage originates from the monarchy. In particular, the turn of the 19th to 20th centuries was undoubtedly a peak in many aspects of arts and culture, and even the population of Vienna was then higher than today. Nonetheless, the monarchy terminated almost hundred years ago and gave way to modernism. All periods of fine arts are represented in Vienna, by architecture as well as in museums. In addition, performing arts and classical music are offered in various places. This presentation will provide an overview of the history of Vienna, the periods of art and where to spot them, with a particular focus on the locations where social events will take place during this conference.
        Speaker: Satoko Friedl
        Slides
    • 6:45 PM 8:00 PM
      Walk to City Hall 1h 15m
    • 8:00 PM 10:00 PM
      Welcome Reception 2h City Hall (Vienna)

      City Hall

      Vienna

    • 9:00 AM 9:45 AM
      Plenary 1 - Electronic Developments for the Experiments at the FAIR Facility Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Luciano Musa (CERN)
      • 9:00 AM
        Electronic Developments for the Experiments at the FAIR Facility 45m
        The FAIR facility, which is being constructed at GSI, Darmstadt, Germany, will provide anti proton and ion beams with unprecedented intensity and quality. Several new or upgraded experiments will study the detailed structure of nuclei, nuclear matter, quark-gluon plasma, and much more. The very high track densities and the lack of fast triggers necessitates self triggered detector readout concepts with high data bandwidth. The talk summarizes the requirements for the detectors, front end electronics and data acquisition and presents some ongoing electronics developments.
        Speaker: Dr Peter Fischer (Physikalisches Institut)
        Slides
    • 9:50 AM 10:40 AM
      A1a - ASICs Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Christophe de La Taille (CNRS LAL Orsay)
      • 9:50 AM
        A CMOS 0.13 um Silicon Pixel Detector Readout ASIC for the PANDA experiment 25m
        The ToPiX ASIC is a custom development for the hybrid pixel sensors of the PANDA experiment Micro Vertex Detector. The ASIC will provide both the time and amplitude informations (via the Time over Threshold technique) of the incoming particle. ToPiX will consist of a matrix of 116x110 cells with a pixel size of 100x100 um2, the column readout logic and two 311 Mbit/s serializers. A reduced scale prototype in CMOS 0.13 um has been designed and is currently under test. The prototype includes eight columns with the full cell analogue and digital circuitry and the end of column readout.
        Speaker: Giovanni Mazza (INFN sez. di Torino, Italy)
        Paper
        Slides
      • 10:15 AM
        The FE-I4 Pixel Readout System-on-Chip resubmission to accommodate the Fast Track IBL plans 25m
        The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the merits imposed by the LHC pixel detectors. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within Insertable B-Layer (IBL). As the IBL schedule was pushed significantly forward, a quick and efficient plan needed to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, design automation issues during this effort will also be addressed.
        Speaker: Dr Vladimir Zivkovic (NIKHEF Institute)
        Paper
        Slides
    • 9:50 AM 10:40 AM
      B1a - Systems, planning, installation, commissioning and running experience Room EI 8

      Room EI 8

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Ken Wyllie (CERN)
      • 9:50 AM
        The Data Acquisition Card for the Large Pixel Detector at the European-XFEL 25m
        The Front End Module (FEM) is a custom on-detector FPGA based digital data acquisition card for the Large Pixel Detector (LPD) currently under construction for the European X-ray Free Electron Laser (XFEL) facility in Hamburg. In normal XFEL operation the LPD detector will generate 10 GBytes/sec of sparsified data for every one mega-pixel of sensor area. Data processed by the FEM is transferred to the off-detector XFEL DAQ via 10 Gbps SFP+ links running UDP/IP based protocols. This paper describes the design of the FEM and the performance of prototype cards.
        Speaker: John Coughlan (STFC Rutherford Appleton Laboratory)
        Paper
        Slides
      • 10:15 AM
        Study of the hybrid controller electronics for the nano-stabilisation of mechanical vibrations of CLIC quadrupoles 25m
        In order to achieve the required levels of luminosity in the CLIC linear collider, mechanical stabilization of quadrupoles to the nanometre level is required. The paper describes a design of hybrid electronics combining an analog controller and digital communication with the main machine controller. The choice of local analog control ensures the required low latency while still keeping sufficiently low noise level. Furthermore, it reduces the power consumption, rack space and cost. Sensitivity to single events is reduced compared to a digital controller. The digital part is required for fine tuning and real time monitoring via digitalization of critical parameters.
        Speaker: Mr Pablo Fernandez Carmona (CERN)
    • 10:40 AM 11:00 AM
      Coffee Break 20m
    • 11:00 AM 12:40 PM
      A1b - ASICs Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Alessandro Marchioro (CERN)
      • 11:00 AM
        The CMS Binary Chip for microstrip tracker readout at the SLHC 25m
        A 130 nm CMOS chip has been designed for silicon microstrip readout at the SLHC. The CBC has 128 channels, and utilises a binary un-sparsified architecture for chip and system simplicity. It is designed to read out signals of either polarity from short strips (capacitances up to ~ 10 pF) and can sink or source sensor leakage currents up to 1 microamp. Details of the design and measured performance will be presented.
        Speaker: Mark Raymond (Imperial College London)
        Paper
        Slides
      • 11:25 AM
        Development of a new Preamplifier-Shaper-Discriminator Chip for the ATLAS Muon Drift Tube Chambers in 130 nm IBM Technology 25m
        We discuss the development and performance of a new analogue and digital readout chip for the Monitored Drift-Tube (MDT) chambers of the ATLAS muon spectrometer using the IBM 130 nm CMOS 8RF-DM technology. The 4-channel Amplifier-Shaper-Discriminator (ASD) chip was designed to match the analogue performance of the presently used device in 0.5 micron Agilent technology which is now obsolete. The new chip development is needed for the replacement of the front-end electronics of the existing MDT chambers by a more radiation hard version as well as for new muon drift-tube chambers with higher rate capability which are needed for high-luminosity upgrades of the Large Hadron Collider (LHC). Very good agreement was found between the simulated and the measured chip performance parameters, in particular the pulse shape, crosstalk, gain uniformity and noise. Results from a first neutron irradiation test will also be discussed.
        Speaker: Dr Hubert Kroha (Max-Planck-Institut fuer Physik, Munich)
      • 11:50 AM
        Associative Memory design for the Fast TracKer processor (FTK) at ATLAS 25m
        We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. We have developed this device using 65 nm technology combining a full custom CAM cell with standard-cell control logic. The customized design maximizes the pattern density, minimizes the power consumption and implements the functionalities needed for the planned Fast Tracker (FTK) [2], an ATLAS trigger upgrade project at LHC. We introduce a new variable resolution pattern matching technique using “don’t care” bits to set the pattern-matching window for each pattern and each layer can be independently.
        Speaker: Dr Matteo Beretta (Istituto Nazionale Fisica Nucleare (INFN) - Laboratori Nazionali di Frascati)
        Slides
      • 12:15 PM
        Low Noise Front End ASIC with Current Mode Active Cooled Termination for the Upgrade of the LHCb Calorimeter 25m
        An integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. The circuit is based on a two fully differential interleaved channel with a first amplifier stage and a switched integrator. It offers an electronically cooled input termination at the input to achieve the stringent noise requirements. Compared to previous designs, its novelty relies in the use of two current feedback loops used to decrease and control the input impedance of a common base transistor. The selected technology corresponds to AMS SiGe BiCMOS 0.35um. Measured noise is below 1 LSB (12 bit scale) and linearity absolute relative error below 1%.
        Speaker: Mr Eduardo Picatoste Olloqui (Universidad de Barcelona)
        Paper
        Slides
    • 11:00 AM 12:40 PM
      B1b - Systems, planning, installation, commissioning and running experience Room EI 8

      Room EI 8

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Ken Wyllie (CERN)
      • 11:00 AM
        The Electronics System of the ALFA Forward Detector for Luminosity Measurements in ATLAS 25m
        The ATLAS Forward Detectors for Measurement of Elastic Scattering and Luminosity (ALFA) have been fully installed during the 2010-2011 winter LHC shutdown. ALFA consists of 8 mini tracking detectors made of 20 planes of scintillating fibers placed in Roman Pot units near the beam and 240m away on both sides of the interaction point. The front-end electronics sit directly on top of the PMTs and has been designed to facilitate the connectivity to the ATLAS control room. The full system consisting of the detectors units, the control electronics and the connections to the ATLAS TTC, DAQ and DCS systems has been successfully tested.
        Speaker: Mr Francis Anghinolfi (CERN)
        Paper
        Slides
      • 11:25 AM
        Electronics for the camera of the First G-APD Cherenkov Telescope (FACT) for ground based gamma-ray astronomy 25m
        Within the FACT project, we construct a new type of camera based on Geiger-mode avalanche photodiodes (G-APDs). Compared to photomultipliers, G-APDs are more robust, need lower operation voltage and have the potential of higher efficiency and lower cost, but were never tested in the harsh environments of Cherenkov telescopes. The FACT camera consists of 1440 G-APD pixels and readout channels, based on the DRS4 analog pipeline chip and commercial Ethernet components. Preamplifiers, trigger system, digitization, slow control and power converters are integrated into the camera. I will present the FACT camera electronics and first experience gained.
        Speaker: Mr Patrick Vogler (ETH Zurich)
        Paper
        Slides
      • 11:50 AM
        Characterisation Of The NA62 GigaTracker End of Column Demonstrator Hybrid Pixel Detector 25m
        The architecture and characterisation of the NA62 GigaTracker End of Column Demonstrator Hybrid Pixel Detector (HPD) will be presented. This detector must perform time stamping to 200 ps (RMS) or better, provide 300 µm pitch position information and operate with a dead time of 1 % or less for 800 MHz−1 GHz beam rate. The demonstrator HPD Assembly comprises a readout chip with a test column of 45 pixels, alongside other test structures, bump bonded to a p-in-n detector 200 µm in thickness. Validation of the performance of the HPD and the time-over-threshold timewalk compensation mechanism with both beam particles and a high precision laser system was performed. Confirmation of better than the required time stamping precision has been demonstrated and will be shown alongside other pertinent results.
        Speaker: Dr Matthew Noy (CERN)
        Paper
        Slides
      • 12:15 PM
        Development of an ATCA IPMI Controller Mezzanine Board and its usage on an ATCA ROD Evaluator board for the ATLAS LAr upgrade 25m
        In the context of the LHC upgrades, a new Read-Out Driver (ROD) board for the ATLAS LAr calorimeter is being developed. xTCA (Advanced/Micro Telecom Computing Architecture) is becoming a standard in high energy physics and is a serious candidate for future readout systems. We will present our current developments to master ATCA and to integrate a large number of very high speed links (96 links/8.5 Gbps) on a ROD Evaluator ATCA board. To manage our ROD Evaluator, we have developed a versatile ATCA IPMI controller for ATCA boards which is FPGA Mezzanine Card (FMC) compliant.
        Speaker: Nicolas Dumont Dayot (LAPP-Laboratoire d'Annecy-le-Vieux de Physique des Particules ()
        Paper
        Slides
    • 12:40 PM 2:00 PM
      Lunch 1h 20m
    • 2:00 PM 2:45 PM
      Plenary 2 - Cryogenic Electronics for Very Large Liquid Argon Neutrino and Nucleon Decay Detectors Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))
      • 2:00 PM
        Cryogenic Electronics for Very Large Liquid Argon Neutrino and Nucleon Decay Detectors 45m
        The Liquid Argon Time Projection Chamber (LAr TPC) technology offers extraordinarily precise event reconstruction and particle identification, as well as scalability to very-large detectors. To go beyond the sensitivities of current experiments for neutrino physics and proton decay, the next generation of liquid argon TPCs are envisioned to be in the range of 20-100 kton. Detectors of this size pose many engineering challenges. The number of sense wires, i.e., input signal channels is expected to be in the range of 3-7 hundred thousand for a 20 kton scale TPC. The location of the signal processing electronics (on the electrodes in LAr vs outside of the cryostat) has a far reaching effect on the cryostat design, on the TPC electrode design (sense wire spacing, wire length and drift distance), and on the electronic noise. All these factors make cryogenic (“cold”) electronics with multiplexed readout essential. In this presentation we summarize the basics of TPC signal formation and electronic noise, present an outline of the readout chain and the measurement results of the front end CMOS ASIC(s) designed and fabricated for this purpose. The results of the R&D on the CMOS electronics show significantly improved transistor properties at LAr temperature (~89K), such as greatly increased transconductance/current ratio gm/I (beneficial for low power design), higher speed and lower noise. We discuss the design guidelines to ensure a long life of MOS transistors. Application of cryogenic electronics to other types of detectors will be summarized.
        Speaker: Veljko Radeka (Brookhaven National Laboratory)
        Slides
    • 2:50 PM 4:05 PM
      A2 - ASICs Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Christophe de La Taille (CNRS LAL Orsay)
      • 2:50 PM
        Development of low power Phase-Locked Loop (PLL) and PLL-based serial transceiver 25m
        The design and measurements results of low power Phase-Locked Loop (PLL) prototype for applications in particle physics detectors readout systems are presented. The PLL is designed and fabricated in 0.35~$\mu$m CMOS technology. First measurements show that the ASIC is fully functional and generates clock in the frequency range 380MHz-1.1GHz. The PLL power consumption at 1~GHz is about 4.5 mW. As one of main goals a transceiver comprising of PLL-based transmitter and receiver with PLL-based clock and data recovery circuit was designed, fabricated and tested. Proper functionality of the transmitter and receiver was verified in the frequency range 650MHz-950MHz.
        Speaker: Mr Jakub Moron (AGH University of Science and Technology)
        Paper
        Slides
      • 3:15 PM
        SKIROC2, a Front-end Chip designed to readout the E-Cal of ILC 25m
        SKIROC (Silikon pin Kalorimeter Integrated ReadOut Chip) is the very front end chip designed for the readout of the Silicon PIN diodes foreseen for the Electromagnetic CALorimeter (ECAL) of the future International Linear Collider. The very fine granularity of the ILC calorimeters implies a huge number of electronics channels (82 millions) which is a new feature of “imaging” calorimetry. Moreover, for compactness, the chips must be embedded inside the detector without any external component making crucial the reduction of the power consumption to 10 µWatt per channel. This is achieved using power pulsing, made possible by the ILC bunch pattern (1 ms of acquisition data for 199 ms of dead time).
        Speaker: Ms Nathalie SEGUIN-MOREAU (OMEGA / IN2P3 - CNRS)
        Paper
        Slides
      • 3:40 PM
        Wideband (500 MHz) 16 bit Dynamic Range Current Mode Preamplifier for the CTA cameras 25m
        A wideband current mode preamplifier with 16 bits dynamic range (DR) is presented. It has been designed for the cameras of the Cherenkov Telescope Array (CTA). A novel current division scheme at the very front end part of circuit splits the input current in to two scaled currents which are connected to independent current mirrors. The mirror of the high gain path comprises a saturation control circuit for accurate current division. Measurement results of an ASIC (Austriamicrosystems 0.35 um SiGe technology) are presented: 500 MHz BW, 16 bits DR, 10 pA/sqrt(Hz) input referred noise and relative linearity error below 3%.
        Speaker: Dr David Gascon (Universidad de Barcelona)
        Paper
        Slides
    • 2:50 PM 4:05 PM
      B2 - Power, Grounding and Shielding Room EI 8

      Room EI 8

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Stephen Quinton (Rutherford Appleton Laboratory)
      • 2:50 PM
        DC/DC ASIC converters in 0.35um CMOS technology 25m
        In view of the upgrade of the LHC experiments, we are developing custom DC/DC converters for a more efficient power distribution scheme. Two new prototypes (AMIS3 and AMIS4) have been integrated in ASICs in the selected 0.35um commercial high voltage technology that has been successfully tested for all radiation effects: TID, displacement damage and Single Event Burnout. While AMIS3 contains small incremental improvements with respect to previous prototypes, AMIS4 is a more complete converter that has been optimized for higher efficiency and improved radiation tolerance. Amongst the new features the most relevant are the presence of internal linear regulators, protection circuits with a state-machine and a new pinout for a modified assembly in package in order to reduce conductive losses. The presentation will illustrate the design of the two prototypes, and show their functional and radiation tests.
        Speaker: Mr Stefano Michelis (CERN)
        Paper
        Slides
      • 3:15 PM
        The Shunt-LDO regulator for powering the upgraded ATLAS pixel detector 25m
        The Shunt-LDO regulator is a new regulator concept which combines a shunt and a Low Drop-Out (LDO) regulator. Designed to match the needs of serially powered detector systems, it can also be used as a pure LDO regulator for general application in powering schemes requiring linear regulation. The flexibility of the design makes the Shunt-LDO a good candidate for use in the powering schemes envisaged for the upgrades of ATLAS pixel detector. Two Shunt-LDO regulators integrated in the prototype of the next ATLAS pixel front-end chip, the FE-I4A, are used to demonstrate the feasibility of the proposed powering solutions.
        Speaker: Laura Gonella (University of Bonn)
        Paper
        Slides
      • 3:40 PM
        ATLAS Upgrade Strip Tracker Stavelets 25m
        The engineering challenges related to the supply of electrical power to future large scale detector systems are well documented. Two options remain under active study in our community, namely serial powering and the use of DC-DC convertors. Whilst clearly different in detail, both have the potential to increase the efficiency of the powering system. The ATLAS Upgrade Strip Tracker Community has constructed a serially powered demonstrator stavelet comprising four silicon strip detector modules using the ABCN-25 ASIC with integrated shunt transistors. At the time of writing, construction of a companion stavelet built using DC-DC converters (provided by the CERN group) is underway. The latest results from both stavelets shall be presented to the workshop.
        Speaker: Mr Peter Phillips (Particle Physics)
        Paper
        Slides
    • 4:05 PM 4:30 PM
      Coffee Break 25m
    • 4:30 PM 5:30 PM
      MUG Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Kostas Kloukinas (CERN)
      • 4:30 PM
        Introduction 5m
        Speaker: Kostas Kloukinas (CERN)
        Slides
      • 4:35 PM
        News on the 130nm technology support 10m
        Speaker: Wojciech Bialas (CERN)
        Slides
      • 4:45 PM
        Design Tools, Flows and Library Aspects during the FE-I4 Implementation on Silicon 15m
        Speaker: Vladimir Zivkovic (NIKHEF Institute)
        Slides
      • 5:00 PM
        Noise and radiation hardness of 65 nm CMOS transistors and pixel front-ends 20m
        Speaker: Massimo Manghisoni (Università degli Studi di Bergamo)
        Slides
      • 5:20 PM
        Access of 65nm technology through CERN 10m
        Speaker: Kostas Kloukinas (CERN)
        Slides
    • 4:30 PM 6:30 PM
      XTCA WG
      Convener: Markus Joos (CERN)
      • 4:30 PM
        Opening 5m
        Speaker: Markus Joos (CERN)
        Slides
      • 4:35 PM
        ATCA developments targeting ITER Fast Plant System Controllers 20m
        Speaker: Bruno Soares Gonçalves (Instituto de Plasmas e Fusão Nuclear)
        Slides
      • 4:55 PM
        Perspectives for xTCA in CMS 20m
        Speaker: Magnus Hansen (CERN)
        Slides
      • 5:15 PM
        Simplified MCH providing clock/controls/DAQ functions 15m
        Speaker: Eric Shearer Hazen (Department of Physics-Boston University)
        Slides
      • 5:30 PM
        Introduction to MicroHAL 10m
        Speaker: Gregory Michiel Iles (Imperial College Sci., Tech. & Med. (GB))
        Slides
      • 5:40 PM
        uTCA evaluation project 10m
        Speaker: Markus Joos (CERN)
        Slides
      • 5:50 PM
        MMC H/W & S/W 15m
        Speakers: Jean-Pierre Cachemiche (Centre de Physique de Particules de Marseille (CPPM)-Faculte de) , Vincent Bobillier (CERN)
        Slides
      • 6:05 PM
        Perspectives for xTCA in ATLAS 20m
        Speaker: Philippe Farthouat (CERN)
        Slides
      • 6:25 PM
        New xTCA Developments at SLAC (by Ray Larsen) 5m
        Speaker: Markus Joos (CERN)
    • 5:30 PM 6:30 PM
      SEU WG Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Jorgen Christiansen (CERN)
      • 5:30 PM
        Introduction 5m
        Speaker: Jorgen Christiansen (CERN)
      • 5:35 PM
        News on SEU in 90nm and 65nm 10m
        Speaker: Dr Sandro Bonacini (CERN)
        Slides
      • 5:45 PM
        SEU test of GBT prototype 10m
        Speaker: Ken Wyllie (CERN)
        Slides
      • 5:55 PM
        SEU measurements of the FEI4 chip 10m
        Speaker: Denis Fougeron (Universite d'Aix - Marseille II (FR))
        Slides
      • 6:05 PM
        SEU protection insertion in Verilog for the ABCN project 10m
        Speakers: Filipe Pereira Alves De Sousa (FEUP Faculdade de Engenharia (FEUP)-Universidade do Porto) , Francis Anghinolfi (CERN)
        Slides
      • 6:15 PM
        FPGA Fault Tolerance for Embedded Systems 11m
        Speaker: Jano Gebelein (Kirchhoff-Institut fuer Physik (KIP)-Ruprecht-Karls-Universitae)
        Slides
    • 6:30 PM 8:00 PM
      Walk to Austrian Academy of Sciences 1h 30m
    • 8:00 PM 10:30 PM
      Classical Concert 2h 30m Austrian Academy of Sciences

      Austrian Academy of Sciences

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
    • 9:00 AM 9:45 AM
      Plenary 3 - Programmable Logic in the 21st Century. Where are we and where are we going? Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Wesley Smith (University of Wisconsin (US))
      • 9:00 AM
        Programmable Logic in the 21st Century. Where are we and where are we going? 45m
        For more than twenty-five years, programmable logic has effectively leveraged Moore’s law to provide steadily increasing device performance, capacity and features, while lowering the cost dramatically. We know that microprocessor power consumption issues forced a radical change in those devices, shifting from faster clock rate to multi-core. Is the same happening to programmable logic? Personal computers and servers drive microprocessor specifications. What drives programmable logic and where will it drive them? This presentation describes the current state of the art of programmable logic and with an understanding of the pressures on the technology, predict how programmable logic will evolve in the near future.
        Speaker: Dr Steve Trimberger (Xilinx Research Labs)
        Slides
    • 9:50 AM 10:40 AM
      A3a - Trigger Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Wesley Smith (University of Wisconsin (US))
      • 9:50 AM
        Performance of the ATLAS Trigger System 25m
        The ATLAS trigger system is responsible for reducing the event rate, from the design bunch-crossing rate of 40 MHz, to an average recording rate of 200 Hz, by selecting signal-like events out of the extremely large background. The ATLAS trigger is designed in three levels. The first-level (L1) is implemented in custom-built electronics, the two levels of the high level trigger (HLT) are software triggers executed on large computing farms. The first-level trigger is comprised of calorimeter, muon and forward triggers to identify event features, such as missing transverse energy, as well as candidate electrons, photons, jets and muons. These inputs are used by the L1 Central Trigger to for a L1 Accept (L1A) decision. L1A and timing information is sent to all sub-detectors. Summary information is sent to the subsequent levels of the trigger system. We will demonstrate that the ATLAS trigger performed smoothly throughout 2010 and 2011, showing the evolution with the increasing LHC luminosity (10^{32}-10^{33} cm^{-1} s^{-1}) in order to maintain a high selection efficiency. A large part of the talk will be devoted to recent improvements of the L1 trigger system.
        Speaker: Dr Carolina Gabaldon Ruiz (CERN)
        Paper
        Slides
      • 10:15 AM
        The ALICE trigger system performance for p-p and Pb-Pb collisions 25m
        The ALICE trigger system in the experimental cavern processes information from triggering detectors at 3 hardware levels in p-p and Pb-Pb collisions. The performance of the system exceeds the specification and many automatic functions have been developed to facilitate work in the control room. The hardware is permanently monitored, and around 1200 counters, with considerable built-in redundancy, are read at regular intervals (once per minute). This provides relevant physics information and also verifies the consistency of the hardware operation. In order to compensate for seasonal drift, the CORDE module has been installed, which allows the LHC clock to be delayed in steps of 10 ps. This paper describes the current status of ALICE trigger system after experience with p-p and Pb-Pb runs, the new firmware developments and the appropriate software for this electronics.
        Speaker: Marian Krivda (University of Birmingham, UK)
        Paper
        Slides
    • 9:50 AM 10:40 AM
      B3a - Programmable Logic, design tools and methods Room EI 8

      Room EI 8

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Magnus Hansen (CERN)
      • 9:50 AM
        A Low-Power Wave Union TDC Implemented in FPGA 25m
        A low-power time-to-digital convertor (TDC) for an application inside vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field-programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurement indicates that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.
        Speaker: Dr Jinyuan Wu (FERMILAB)
        Paper
        Slides
      • 10:15 AM
        A 32-Channel High Resolution (<15 ps RMS) Time-to-Digital Converter (TDC) in a Field Programmable Gate Array (FPGA) 25m
        A 32-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine-time calculations are achieved by using the dedicated carry-chain lines. A low latency (30 ns) encoder handles the conversion of the fine time measurement. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of temperature and power supply dependency bin-by-bin calibration is applied. The time interval measurements are done using 2 channels. RMS and the time resolution of channels are calculated for different time intervals and a minimum of 15 ps RMS on two channels, yielding 10.6 ps (15ps/√2) time resolution on a single channel is achieved.
        Speaker: Mr Cahit Ugur (GSI Helmholtzzentrum für Schwerionenforschung)
        Slides
    • 10:40 AM 11:00 AM
      Coffee Break 20m
    • 11:00 AM 12:40 PM
      A3b - Trigger Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Emilio Petrolo (Universita e INFN, Roma I (IT))
      • 11:00 AM
        CMS Calorimeter Trigger Phase 1 Upgrade 25m
        We present a design for the Phase-1 upgrade of the CMS calorimeter trigger system composed of FPGAs and Multi-GBit/sec links that adhere to the micro-TCA crate Telecom standard. The upgrade calorimeter trigger will implement algorithms that create collections of isolated and non-isolated electromagnetic objects, isolated and non-isolated tau objects and jet objects. The algorithms are organized in several steps with progressive data reduction. These include a particle cluster finder that reconstructs overlapping clusters of 2x2 calorimeter towers and applies electron identification, a cluster overlap filter, a particle isolation determination, jet reconstruction, particle separation and sorting.
        Speaker: Dr Pamela Klabbers (University of Wisconsin)
        Paper
        Slides
      • 11:25 AM
        Upgrade of the ATLAS Level-1 Muon Trigger for High Luminosities Using the Precision Muon Drft Tube Chambers 25m
        The upgrade of the LHC towards higher luminosity requires improved L1 trigger selectivity in order to keep the maximum total trigger rate at about 100 kHz. In the L1 muon trigger system this necessitates an increase of the pT threshold for single muons. Due to the limited spatial resolution of the trigger chambers, however, the selectivity for tracks above about 20 GeV/c is insufficient for an effective reduction of the L1 rate. We propose to used the precise track coordinates of the Monitored Drift Tube chambers in the ATLAS muon spectrometer for a decisive improvement of the L1 muon trigger pT resolution and selectivity. The implementation in the ATLAS trigger system, the fast track segment identification and the required latency will be discussed.
        Speaker: Dr Hubert Kroha (Max-Planck-Institut fuer Physik, Munich)
        Paper
        Slides
      • 11:50 AM
        A demonstration of a Time Multiplexed Trigger for CMS 25m
        A novel approach to first-level hardware triggering has been studied and a prototype system built. Calorimeter trigger primitive data (~5 Tb/s) are reorganised and time-multiplexed so that a single processing node (FPGA) may access the data corresponding to the entire detector for a given bunch crossing. This provides maximal flexibility in the construction of new trigger algorithms, which will be an important factor in ensuring adequate trigger performance at the very high levels of background expected at the upgraded LHC. A vertical slice of the first level trigger chain is presented, including: the time-multiplexing system, algorithm processors, DAQ functionality and subsequent demultiplexing. The challenges of building what is essentially a 5 Tb/s image processor are explored, along with the potential performance and operational benefits.
        Speaker: Dr Gregory Michiel Iles (Imperial College Sci., Tech. & Med.)
        Paper
        Slides
      • 12:15 PM
        Upgrade plans for the CMS Trigger Drift Tube Track Finder electronics 25m
        The present CMS Trigger Drift Tube Track Finder Unit was designed between 2003 and 2006. The long Shutdown planned for 2016-2017 gives an opportunity to perform a basic upgrade of this system. The rapid technology development allows us to redesign the electronic groups and structures in such a way that a smaller, more reliable facility with easier control and reduced maintenance can be built.
        Speaker: Janos Ero (Institut fuer Hochenergiephysik (HEPHY))
        Slides
    • 11:00 AM 12:40 PM
      B3b - Programmable Logic - Systems Room EI 8

      Room EI 8

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Dr Markus Friedl (Institut fuer Hochenergiephysik (HEPHY)-Oesterreichische Akadem)
      • 11:00 AM
        A Readout System-on-Chip for a Cubic Kilometre Submarine Neutrino Telescope 25m
        This contribution reports on the read-out system of the future KM3NeT undersea network of several thousands of synchronized optical detecting nodes. Each node embeds a specifically designed fully integrated communicating system based on Xilinx FPGA SoC technology. It runs the VxWorks real-time OS and DAQ software designed within the ICE middleware framework resulting in a highly flexible, controllable and scalable distributed application. Clock distribution and delay calibration over customized fixed latency gigabit Ethernet links enables synchronous time stamping of events with sub-nanosecond precision.
        Speaker: Mr Hervé Le Provost (IRFU-CEA)
        Paper
        Slides
      • 11:25 AM
        Data acquisition electronics and reconstruction software for real time 3D track reconstruction within the MIMAC project 25m
        Directional detection of non-baryonic Dark Matter requires 3D reconstruction of low energy nuclear recoils tracks. A gaseous micro-TPC matrix, filled with either 3He, CF4 or C4H10 has been developed within the MIMAC project. A dedicated acquisition electronics and a real time track reconstruction software have been developed to monitor a 512 channel prototype. This auto-triggered electronic uses embedded processing to reduce the data transfer to its useful part only, i.e. decoded coordinates of hit tracks and corresponding energy measurements. An acquisition software with on-line monitoring and 3D track reconstruction is also presented.
        Speaker: Mr Olivier Bourrion (Laboratoire de Physique Subatomique et de Cosmologie (LPSC)-Univ)
        Paper
        Slides
      • 11:50 AM
        THE ANTARES NEUTRINO DETECTOR INSTRUMENTATION 25m
        ANTARES is the First full operational and the largest neutrino telescope in the Northern hemisphere. Located in the Mediterranean Sea, it consists of a 3D array of 885 photomultiplier tubes (PMTs) arranged in 12 detection lines (25 storeys each), able to detect the Cherenkov light induced by upgoing relativistic muons produced in the interaction of high energy cosmic neutrinos with the detector surroundings (or volume). Among its physics goals, the search for neutrino astrophysical sources and the indirect detection of dark matter particles coming from the sun, are of particular interest. To reach that, a good accuracy in the muon tracks reconstruction is mandatory, so several calibration systems as timing and positioning systems have been developed. In this talk we will present the design of the detector, calibration systems and associated equipment, along with a summary of the lessons learned for the future cubic kilometer detector in the Mediterranean sea, KMN3NeT.
        Speaker: Mr Harold Yepes Ramirez (IFIC-ANTARES)
        Paper
        Slides
      • 12:15 PM
        The Sound Emission Board of the KM3NeT acoustic positioning system 25m
        We describe the sound emission control board of an acoustic positioning system necessary to triangulate flexible optical detection lines in the KM3NeT future deep sea neutrino telescope. Such a positioning system must log the positions of optical sensors for Cherenkov radiation emitted in sea water to precisions of ~10cm, over a >1 km3 instrumented volume. This will be achieved by acoustic triangulation of sound transit time differences between fixed seabed emitters and receiving hydrophones attached to kilometer-scale vertical flexible structures carrying the optical sensors. New custom-built sound emission boards will generate the time stamped sound bursts used in this system.
        Speaker: Mr Carlos David Llorens (Universidad Politécnica de Valencia representing the KM3NeT Consortium)
        Paper
        Slides
    • 12:40 PM 2:00 PM
      Lunch 1h 20m
    • 2:00 PM 2:45 PM
      Plenary 4 - 3D integration of pixel detectors at VTT Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      • 2:00 PM
        3D integration of pixel detectors at VTT 45m
        Vertical (3D) integration using Through Silicon Vias (TSV) is gaining lot of attention within electronics industry. 3D integrated structures should enhance electrical performance of electronic devices, boost up device miniaturization, and enable new designs and stacks of device layers made with heterogeneous technologies. For pixel detectors, 3D integration using TSVs in combination with edgeless sensors is believed to solve the problem regarding the building large panels with minimal gaps between the individual tiles. VTT is doing R&D in the field of edgeless sensors and advanced interconnects. This presentation gives updates on the separate activities at VTT which are needed for fabrication of 3D integrated pixel detectors using Cu TSVs.
        Speaker: Sami Vaehaenen
        Slides
    • 2:50 PM 4:05 PM
      A4 - ASICs Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      • 2:50 PM
        A Reticle Size CMOS Pixel Sensor Dedicated to the STAR HFT Upgrade 25m
        ULTIMATE is a reticle size CMOS Pixel Sensor (CPS) designed to meet the requirements of the STAR pixel detector (PXL). It includes a pixel array of 928 rows and 960 columns with a 20.7µm pixel pitch, providing a sensitive area of ~3.8cm². Based on the sensor designed for the EUDET beam telescope, the device is a binary output sensor with integrated zero suppression circuitry featuring a 320 Mbps data throughput capability. It was fabricated in a 0.35µm OPTO process early in 2011. The design and preliminary test results, including charged particle detection performances measured at the CERN-SPS, will be presented.
        Speaker: Dr Hung Pham (DRS-IPHC (IReS), University of Strasbourg, CNRS-IN2P3)
      • 3:15 PM
        Radiation Tolerant Low Power 12-bit ADC in 130 nm CMOS Technology 25m
        Electronic circuits submitted to high doses of radiation are prone to functional failures. Due to the high cost of currently available radiation hard technologies, alternative design approaches, resort to available, yet less costly and higher performance, commercial CMOS technologies. To improve radiation tolerance within these technologies specific design and layout methodologies are explored. In this work the design of a radiation tolerant low power 12-bit analogue to digital dual-ramp integrating converter (ADC) in 130 nm CMOS technology is presented. The rationale behind the selection of this architecture is described and details of the design of the ADC circuit elements are provided.
        Speaker: Filipe Pereira Alves De Sousa (Univ. do Porto-Unknown-Unknown)
        Slides
      • 3:40 PM
        FF-EMU: a radiation tolerant ASIC for the distribution of timing, trigger and control signals in the CMS End-Cap Muon detector 25m
        A radiation tolerant integrated circuit for the distribution of clock, trigger and controls in the Front-End electronics of the CMS End-Cap Muon detector has been developed in the IBM CMOS 130nm technology. The circuit houses transmitter and receiver interfaces to serial links implementing the FF-LYNX protocol that allows the integrated transmission of triggers and data frames with different latency constraints. Command encoder and decoder modules associate transitions in trigger and control signals to data frames. The circuit architecture and results of test and characterization of the prototypes will be presented.
        Speaker: Mr Guido Magazzu (UCSB/INFN)
        Paper
        Slides
    • 2:50 PM 4:05 PM
      B4 - Power, Grounding and Shielding Room EI 8

      Room EI 8

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      • 2:50 PM
        A DC-DC converter based powering scheme for the upgrade of the CMS pixel detector 25m
        Around 2016, the pixel detector of the CMS experiment will be upgraded. The amount of current that has to be provided to the front-end electronics is expected to increase by a factor of two. Since the space available for cables is limited, this would imply unacceptable power losses in the available supply cables. Therefore it is foreseen to place DC-DC converters close to the front-end electronics, allowing to provide the power at higher voltages and thereby to facilitate the supply of the required currents with the present cable plant. This talk introduces the foreseen powering scheme of the pixel upgrade. For the first time, system tests have been conducted with pixel barrel sensor modules, radiation tolerant DC-DC converters and the full power supply chain of the pixel detector. In addition, studies of the stability of different powering schemes under various conditions are summarized. In particular the impact of large and fast load variations, which are related to the bunch structure of the LHC beam, has been studied.
        Speaker: Mr Jan Sammet (RWTH Aachen University)
        Paper
        Slides
      • 3:15 PM
        Electromagnetic Compatibility of CMS Infrastructure and Detector Electronics 25m
        The electronic systems of modern high-energy physics detectors are often built with electromagnetic compatibilty issues as an important part of the requirements driving the design of the detector. The CMS experiment at CERN has an appreciable amount of electronic infrastructure not usually found in previous generations of high-energy physics detectors. Over more than a year of CMS running, we have had the opportunity to observe several instances of unexpected interactions with infrastrucutre electronics. This presentation will examine the mechanisms and consequences of these interactions, as well as considering the coordination of infrastructure and detector electronics design.
        Speaker: Dr Sergei Lusin (CERN)
        Paper
        Slides
      • 3:40 PM
        Control, monitoring and safety aspects of power distribution in the ATLAS experiment 25m
        The Atlas infrastructure, including also power distribution, has been built from scratch for the purpose of the LHC experiment. This provided more freedom and helped to deploy modern solutions. It this document will be presented examples of different approaches to implement electrical distribution. Ways to achieve the expected level of control will be demonstrated, statistics presenting usage of the control system will be given. Applications developed to enrich monitoring of the electrical infrastructure including also quality of the powering network will be shown. Characteristics of applications focused on safety of the Atlas rack’s supply will be demonstrated.
        Speaker: Wieslaw Iwanski (CERN/INP PAN Cracow)
        Paper
        Slides
    • 4:05 PM 4:30 PM
      Coffee Break 25m
    • 4:30 PM 5:55 PM
      OPTO WG: Experience with running systems Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Conveners: Francois Vasey (CERN) , Tobias Flick (Bergische Universitaet Wuppertal)
      • 4:30 PM
        Introduction: What has been presented in March miniworkshop, what talks and posters are foreseen in opto session 10m
        Speaker: Tobias Flick (Bergische Universitaet Wuppertal (DE))
        Slides
      • 4:40 PM
        LHCb: Status of the optical system / optical system upgrades and associated developments 15m
        Speaker: Ken Wyllie (CERN)
        Slides
      • 4:55 PM
        CMS Tracker: Status of the optical system / optical system upgrades and associated developments 15m
        Speaker: Dr Jan Troska (CERN)
        Slides
      • 5:10 PM
        CMS ECAL: Status of the optical system / optical system upgrades and associated developments 15m
        Speaker: Alexander Singovski (University of Minnesota (US))
        Slides
      • 5:25 PM
        CMS HCAL: Status of the optical system / optical system upgrades and associated developments 15m
        Speaker: Eric Shearer Hazen (Boston University (US))
        Slides
      • 5:40 PM
        ATLAS LArg: Status of the optical system / optical system upgrades and associated developments 15m
        Speaker: Stefan Simion (Universite de Paris-Sud 11 (FR))
    • 4:30 PM 6:45 PM
      POWER WG Room EI 8

      Room EI 8

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Conveners: Magnus Hansen (CERN) , Philippe Farthouat (CERN)
      • 4:30 PM
        Introduction 5m
        Speakers: Magnus Hansen (CERN) , Philippe Farthouat (CERN)
      • 4:35 PM
        status and plans of the EMC CMS-tracker upgrade project 20m
        Speaker: Maria Cristina Esteban Lallana (Instituto Tecnologico de Aragon)
        Slides
      • 4:55 PM
        Status of the switched capacitor DC-DC converters for the upgraded LHC trackers 20m
        Speaker: Michal Bochenek (Conseil Europeen Recherche Nucl. (CERN))
        Slides
      • 5:15 PM
        DC-DC developments: future plans 20m
        Speaker: Stefano Michelis (CERN)
        Slides
      • 5:35 PM
        DC-DC modules: gained experience, material budget improvements, grounding aspects 20m
        Speakers: Georges Blanchot (CERN) , Stefano Michelis (CERN)
        Slides
      • 5:55 PM
        Integrated DC-DC converter in the FE-I4 20m
        Speaker: Laura Gonella (Universitaet Bonn (DE))
        Slides
      • 6:15 PM
        Co-ordinated developments for bulk supplies? First discussion 15m
        Speaker: Philippe Farthouat (CERN)
        Slides
      • 6:30 PM
        Discussion 15m
    • 5:55 PM 6:30 PM
      OPTO WG: Environmental resistance tests Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Conveners: Francois Vasey (CERN) , Tobias Flick (Bergische Universitaet Wuppertal)
      • 5:55 PM
        Introduction: What has been presented i March miniworkshop, what talks and posters are foreseen in opto session 5m
        Speaker: Tobias Flick (Bergische Universitaet Wuppertal (DE))
        Slides
      • 6:00 PM
        CERN irradiation studies 15m
        Speaker: Dr Jan Troska (CERN)
        Slides
      • 6:15 PM
        SMU cryogenic tests 15m
        Speaker: Tiankuan Liu (Southern Methodist University (US))
        Slides
    • 9:00 AM 9:45 AM
      Plenary 5 - Silicon photonic devices Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      • 9:00 AM
        Silicon photonic devices 45m
        Silicon photonics has received a growing interest in the last years due to the possibility to realize strongly miniaturized photonic circuits using CMOS-compatible techniques and processes, and to the possible forthcoming integration of optical functions with electronics on the same chips. Passive and active devices have been demonstrated to distribute and manipulate light using a vast panel of physical effects. Among the required functionalities, significant breakthroughs have been recently demonstrated in the fields of light modulation and detection using group-four (germanium-rich) materials. We will review recent progress in the related fields and give some possible future prospects.
        Speaker: Dr Eric CASSAN (IEF - Univ. Paris Sud Orsay)
        Slides
    • 9:50 AM 10:40 AM
      A5a - Packaging and Interconnects Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Jorgen Christiansen (CERN)
      • 9:50 AM
        Microfluidic cooling for detectors and electronics 25m
        Micro-channel cooling is gaining considerable attention as an alternative technique for cooling of high energy physics detectors and front-end electronics. We are evaluating this technology for future tracking devices where material budget limitations are a major concern. Micro channel cooling is currently under investigation as an option for the cooling of the NA62 Gigatracker silicon pixel detector and its front-end electronics where a micro-fabricated cooling plate would stand directly in the beam. Other possible applications are also being studied in the context of LHC detectors upgrades. In this paper, the current status of this R&D at CERN will be presented.
        Speaker: Paolo Petagna (CERN)
        Paper
        Slides
      • 10:15 AM
        Progress on a Si-W ECAL Detection and Readout Interconnects 25m
        The SiD collaboration is developing a Si-W sampling electromagnetic calorimeter, with anticipated application for the International Linear Collider. Assembling the modules for such a detector will involve bonding technologies for the interconnects, especially silicon detector wafer to a flex-cable readout bus attachments. We review the interconnect technologies involved, including oxidation removal processes, pad surface preparation, solder ball selection and placement, and bond quality assurance. Our results will show that solder ball bonding will be a successful technique for the Si-W ECAL. In addition, we report on novel alternatives, including anisotropic conducting film and its use for moderate pitch interconnects.
        Speaker: Mr Michael Woods (University of California Davis)
        Paper
        Slides
    • 9:50 AM 10:40 AM
      B5a - Optoelectronics and Links Room EI 8

      Room EI 8

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))
      • 10:15 AM
        A Network Architecture for Bidirectional Data Transfer in High-Energy Physics Experiments Using Electroabsorption Modulators 25m
        The forthcoming increase of rate of data production and radiation levels, associated with the transition to HL-LHC, necessitates a readout link upgrade. This upgrade is also an opportunity to move to a more efficient network infrastructure and to introduce new technologies and it is in light of this that we explore the possibility of using a unified architecture based on Reflective Electroabsorption Modulators. We evaluate the performance of this new architecture and investigate the way performance degradation factors, including the imperfect extinction ratio and reflection feedback, affect it. We also report on the optimization of operating parameters, such as the modulation voltage and operating wavelength.
        Speaker: Mr Spyridon Papadopoulos (CERN)
    • 10:40 AM 11:00 AM
      Coffee Break 20m
    • 11:00 AM 12:40 PM
      A5b - Packaging and Interconnects - Radiation tolerant components and systems Rom EI 7

      Rom EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Jorgen Christiansen (CERN)
      • 11:00 AM
        SLID-ICV interconnection technology for the ATLAS pixel upgrade at SLHC 25m
        We will report on the characterization of pixel modules composed of 75 microns thick n-in-p sensors and ATLAS FE-I3 chips, interconnected via the SLID (Solid Liquid Inter-Diffusion) technology. This technique, developed at Fraunhofer-EMFT, is employed as an alternative to the bump-bonding process. These modules have been designed as a demonstration of a very compact detector to be employed in the future ATLAS pixel upgrades, making use of vertical integration technologies. This module concept also envisages Inter-Chip-Vias (ICV)to extract the signals from the backside of the chips, thereby achieving a higher fraction of active area with respect to the present pixel module design. In the case of the demonstrator module ICVs are etched into the original wire bonding pads of the FE-I3 chip. In the modules with ICVs the FE-I3 chips will be thinned down to 50 um. The status of the ICV preparation will be presented.
        Speaker: Dr Anna Macchiolo (Max-Planck-Institut fuer Physik)
        Slides
      • 11:25 AM
        Characterization of a commercial 65nm CMOS technology for SLHC applications. 25m
        The radiation characteristics with respect to Total Ionizing Dose (TID) of a 65 nm CMOS technology has been investigated. Single transistor structures of a variety of dimensions and several basic circuits were designed and fabricated. The circuits include a 64-kbit shift-register, a 9-kbit SRAM, a ring-oscillator, a low noise preamplifier, a low-power discriminator and two 6-bit DACs with different architectures to compare matching properties at this node. The test chips were irradiated up to 100 Mrad with an X-ray beam and the corresponding threshold shifts and leakage currents measured.
        Speaker: Dr Sandro Bonacini (CERN)
        Paper
        Slides
      • 11:50 AM
        Radiation Tolerance of Readout Electronics for Belle II 25m
        Readout and digitization electronics of upgraded B-factory detector Belle II will be located at the detector side to reduce number of analog cables. The digitized signals are transmitted out over optical serial links. The on-detector electronics is expected to suffer about 10¹² neutrons per year with kinetic energy peaking around 5 MeV. In our studies bombarding a prototype on-detector electronics equipped with FPGAs and optical transceivers at a test beam line and a nuclear reactor, we conclude the radiation tolerance of our on-detector electronics under the expected severe radiation condition. We report our studies and conclusions.
        Speaker: Dr Takeo Higuchi (KEK)
        Paper
        Slides
      • 12:15 PM
        nanoFIP: a radiation tolerant FPGA-based WorldFIP agent 25m
        WorldFIP is a deterministic fieldbus used in the LHC for the communication with a variety of systems. There are more than 10.000 WorldFIP agents installed all around the LHC tunnel and exposed to a complex radiation field. A new customized version of WorldFIP agents, the nanoFIP, housed in an Actel ProASIC3 FPGA, has been developed at CERN in cooperation with the industry. The paper describes the project’s strategy towards radiation tolerance and the results of the radiation testing of the nanoFIP chip with a 230 MeV proton beam at the PSI facility.
        Speaker: Ms Evangelia GOUSIOU (CERN)
        Paper
        Slides
    • 11:00 AM 12:40 PM
      B5b - Optoelectronics and Links Room EI 8

      Room EI 8

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Francois Vasey (CERN)
      • 11:00 AM
        VCSEL Reliability Studies and Development of Robust VCSEL Arrays 25m
        Severe problems with VCSEL reliability have been observed in ATLAS operation. ATLAS has developed the use of Optical Spectrum Analysers as a sensitive indication of VCSEL damage. These studies and detailed microscopic investigations have shown that the observed VCSEL reliability issues have been caused by moderate levels of humidity combined with the use of non-hermetic packages. Long term damp heat tests of VCSEL arrays produced by AOC and ULM which have been optimised for humidity resistance will be presented. The ULM arrays were packaged in a very compact semi-hermetic package which could be interesting for future HEP experiments.
        Speaker: Dr Anthony Weidberg (Nuclear Physics Laboratory)
        Paper
        Slides
      • 11:25 AM
        The radiation induced attenuation of specific single-mode and multi-mode optical fibres below -20°C exposed to full HL-LHC doses at a dose rate of 1 kGy/hr 25m
        The Versatile Link (VL) project is developing a high-speed optical link for the HL-LHC. 850 nm VCSELs are more radiation-hard than 1310 nm EELs. Previous tests on multimode fibres at -25°C at 27 kGy/hr showed unacceptable radiation induced absorption. We have developed a CO2 cooling system which will be used in late June to irradiate cold fibres at low dose rates (1 kGy/hr) to the full HL-LHC dose (300 kGy). These results will determine the viability of an 850nm VL solution with fibres within the cold volume.
        Speaker: Mr David Hall (University of Oxford)
        Paper
        Slides
      • 11:50 AM
        First test results with the Gigabit Link Interface Board (GLIB) 25m
        We have designed and built an FPGA-based platform for users of high speed optical links in high energy physics experiments. The Gigabit Link Interface Board (GLIB) serves both as a platform for the evaluation of optical links in the laboratory as well as a triggering and/or data acquisition system in beam or irradiation tests of detector modules. The GLIB is a double width Advanced Mezzanine Card (AMC) that is used either stand-alone or inside a μTCA crate. This paper presents test results with the first GLIB prototypes delivered in January 2011 and reports on a setup demonstrating its use in a GBT-based system.
        Speaker: Dr Paschalis Vichoudis (CERN)
        Paper
        Slides
      • 12:15 PM
        Versatile Transceiver Development Status 25m
        The Versatile Link common project is developing optical link architectures and components to be used for readout and control in future HL-LHC experiments. The on-detector opto-electronic module, the Versatile Transceiver (VTRx), is derived from an industry standard module type and is adapted through minimal customization to the requirements dictated by the HL-LHC-specific front-end environment. In this contribution we present the methods and results of the functional tests carried out on the transceiver components. We summarize the development status of the different VTRx variants and we show the results obtained using the packaged VTRx module.
        Speaker: Csaba Soos (CERN)
        Paper
        Slides
    • 12:40 PM 2:00 PM
      Lunch 1h 20m
    • 2:00 PM 2:45 PM
      Plenary 6 - Organic and Printed Large-area Electronics: Disruptive Technologies for Innovative Applications Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Alessandro Marchioro (CERN)
      • 2:00 PM
        Organic and Printed Large-area Electronics: Disruptive Technologies for Innovative Applications 45m
        Organic electronics is manufactured with carbon-based semiconductors that are processed at low temperature, and thus can be deployed on thin, flexible substrates like plastic foils and paper. Organic semiconductors are often available as ink-like solutions, thus high throughput fabrication of electronics using processes normally designed for graphical printing is feasible and has been the objective of an intense research activity [1-3]. The material properties of organic semiconductors have been improving at an impressive pace in the last two decades: from mobility in the order of 10-5cm2/Vs we reach now state of the art values beyond 1cm2/Vs. Traditionally n-type semiconductors were very sensitive to environmental influence, and thus only p-type transistors were air-stable. This has also changed in the last five years, leading to the development of air-stable complementary organic technologies offering both n and p transistors [4]. Organic transistors are made patterning staggered thin-films of conductive, semi-conductive and insulating materials, and are thus called “thin film” transistors. Device stacks where the gate is either the lowest or the topmost contact are equally common, and the mutual position of source and drain with respect to the semiconductor layer may vary, providing different device geometries. Due to the limited stability traditionally available from n-type semiconductors, circuits based on organic TFTs (OTFTs) have been mostly developed with p-only technologies. This, together with fact that no standard method exists to precisely dope organic semiconductors and thus to control the threshold voltage of OTFTs, led to a rather slow development of circuits based on organic transistors [5]. The appearance of double-gate structures, which allow electrical tuning of the threshold, together with the availability of the first complementary technologies, has given a strong impulse to circuit development in the last couple of years. Nowadays digital circuits with a complexity level of about five thousands gates [6] are state of the art, together with elementary analogue functions and data converters with an effective resolution of 4 bit [7]. Applications of organic electronics cover all domains where mechanical flexibility, large area capability and very high production throughput, together with potential low cost per area, are of interest. Flexible and roll-up displays, item-level RFID tags, intelligent sensor labels, OLED lighting, solar cells, etc. are some examples. For particle physics applications the large area capability could be a very interesting asset, but the intrinsic thin-film form factor of organic electronics makes it rather unsuited for particle detectors. Future developments will probably see an increasing popularity of (n-type) metal oxides (like ZnO or GaInZnO) used as high mobility, large-area compatible, low-temperature semiconductors, probably coupled to organic materials as p-type semiconductors. The presentation will give an overview of devices, circuits and applications based on OTFTs, and will stimulate a debate on the possible use of this technology in high energy physics. Acknowledgements This work has been partly funded in the frame of the European FP7 project COSMIC (grant agreement n° 247681) and it is supported by the Dutch Technology Foundation STW, which is the applied science division of NWO, and the Technology Programme of the Dutch Ministry of Economic Affairs. References [1] A. Knobloch et al., “Fully printed integrated circuits from solution processable polymers,” Jour. Appl. Phys., vol. 96, no. 4, p. 2286-2291, 2004. [2] V. Subramanian et al. “Printed RF tags and sensors: the confluence of printing and semiconductors” Proceedings of the 5th European Microwave Integrated Circuits Conference, p. 258-261, 2010. [3] Taik-Min Lee et al. “Development of a gravure offset printing system for the printing electrodes of flat panel display”. Thin Solid Films 518 p. 3355–3359, 2010. [4] A. Daami et al. “Fully printed organic CMOS technology on plastic substrates for digital and analog applications”, Proc. ISSCC 2011, p. 328-320, 2011. [5] E. Cantatore et al.“A 13.56-MHz RFID system based on organic transponders”, JSSC vol. 42, no. 1, pp. 84–92, 2007. [6] K. Myny et al. “An 8b organic microprocessor on plastic foil”, Proc. ISSCC 2011, p. 322-324, 2011. [7] H. Marien et al."A Fully Integrated ADC in Organic Thin-Film Transistor Technology on Flexible Plastic Foil," JSSC vol.46, no.1, p.276-284, 2011.
        Speaker: Dr Eugenio Cantatore (Eindhoven University of Technology)
    • 2:45 PM 3:30 PM
      Plenary 7 - Radiation Damage to Electronics at the LHC – A First Analysis Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Alessandro Marchioro (CERN)
      • 2:45 PM
        Radiation Damage to Electronics at the LHC – A First Analysis 45m
        A large spectrum of equipment and electronics is exposed to radiation around the various underground areas of the CERN ‘Large Hadron Collider’ (LHC). In the current configuration, LHC alcoves equipped with commercial or not specifically designed electronics are mostly affected by the risk of ‘Single Event Effects’ (SEE), whereas electronics installed in the LHC tunnel will in the long-term also suffer from cumulative damage due to accumulated dose or displacement damage. While for the tunnel equipment radiation tests were performed and radiation tolerant design criteria were already taken into account during the LHC construction phase, most of the equipment placed in adjacent and partly shielded areas was not conceived nor tested for their current radiation environment. Given the large amount of electronics being installed in these areas, the risk of radiation-induced damage or malfunctioning has to be minimized as much as possible in order to allow for both safe and efficient LHC operation. To carefully analyze the situation, in 2008 a ‘Radiation Damage to Electronics’ (R2E) study group was created, complemented by the R2E mitigation project in 2010 in order to mitigate all risks related to radiation induced failures and possibly limiting future LHC performance. The preparation, study and optimization of short/mid- and long-term mitigation actions require a careful analysis of the: 1. radiation levels and particle energy spectra, as well as their evolution with LHC operation based on both detailed Monte-Carlo simulations and dedicated measurements. 2. inventory of installed electronics (designed, COTS) and failure consequences 3. expected radiation sensitivity, failure cross-section and respective failure rates 4. early monitoring and optimization possibilities 5. evaluation of mitigation options, consisting of: • early actions • shielding (simple + complex) • relocation • radiation tolerant by design • civil engineering options • other options 6. analysis of early LHC operation 7. evaluation and comparison of required and available resources This paper summarizes the chosen approach for the LHC, presents the encountered difficulties and summarizes the obtained experience concerning the main requirements: (a) the radiation field & related calculations, monitoring and benchmarking; (b) the particularity of commercial equipment/systems and their use for the accelerator; and (c) the required radiation tests, as well as respective test areas and facilities. A special focus will be put on the respective lessons learned, as well as on the observations made during early LHC operation.
        Speaker: Dr Markus Brugger (CERN)
        Slides
    • 3:30 PM 4:00 PM
      Coffee Break 30m
    • 4:00 PM 6:30 PM
      Posters
      • 4:00 PM
        A 9-Channel, 100ps LSB Time-to-Digital Converter for the NA62 Gigatracker Readout ASIC (TDCpix) 2h 30m
        The NA62 experiment needs to provide time stamping of individual particles to 200ps-rms or better per station. Bump-bonded to the pixel sensor each ASIC serves an array of 40 columns x 45 pixels. Discriminated signals from each pixel are sent to the lower edge of the ASIC to an array of time-to-digital converters (TDCs). The outputs of 5 pixels are multiplexed together yielding a total of 9 channels needed per column. A multilevel approach based on a delay-locked-loop (DLL) is used to achieve a constant time binning of 100ps over process-voltage- temperature (PVT) variations. Limited implementation space as well as a large amount of digital logic make the integration especially challenging. Simulation results show that an average rms time resolution of 35ps and a nominal power consumption of the TDC better than 3: 5mW /Channel is achieved. Finally, in the scope of the TDCpix a total of 40 TDCs are embedded to serve all 40 Columns. This contribution will present the implementation, simulation results and design challenges of the TDCpix TDC.
        Speaker: Mr Lukas Perktold (CERN)
        Paper
        Slides
      • 4:00 PM
        A fast and low noise charge sensitive preamplifier in 90 nm CMOS technology 2h 30m
        An integrated charge sensitive preamplifier was designed in 90 nm CMOS technology. The chip is part of the R&D effort towards the upgrade of the pixel sensors of the CMS detector. It was submitted in april 2010, and was received and tested in autumn 2010. In the design of the amplifier block, a single ended structure was preferred over a differential one, in order to achieve a lower noise. Three gain stages were put in series to obtain a high open loop gain at high frequency. The gain of the third stage was made adjustable, in order to change the overall open loop gain to match the closed loop gain. Thanks to the high speed MOS transistors and low parasitic capacitances, the feed-backed preamplifier can operate at a frequency above 100 MHz, with transistion edges of about 5 ns. The input-referred RMS noise is 400 e^- with a 1 pF detector over the full preamplifier bandwidth, allowing to read out charge pulses of a few ke^-. Power consumption is less than 5 mW for the single channel prototype.
        Speaker: Mr Claudio Gotti (INFN Milano Bicocca and Università di Firenze)
        Paper
        Poster
      • 4:00 PM
        A front-end chip development for the sLHC CMS Silicon Strip Tracker 2h 30m
        FEAFS chip has been designed for a future sCMS Silicon Strip Tracker. Its primary function is to provide a 40 MHz selective readout of particle hits useful to establish the 100kHz hardware trigger of the experiment. To achieve this goal, the chip identifies clusters of limited number of activated strips and correlated in position in two closely superimposed sensors connected to the same chip. These data are sent on a shared link with the full detector read-out of trigger-accepted events. FEAFS chip has been developed in IBM 0.13µm technology. This poster presents the design of the chip and test results.
        Speakers: Dr Hervé Chanal (Laboratoire de Physique Corpusculaire de Clermont-Ferrand) , Mr Yannick Denis Zoccarato (Institut de Physique Nucleaire de Lyon (IPNL)-Universite Claude)
        Paper
        Slides
      • 4:00 PM
        A multichannel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module 2h 30m
        The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted-clock-sampling method. A particular challenge of this algorithm is the predictable placement of the logic components and the uniform routing inside the FPGA. We present measurement results for the time resolution, the differential nonlinearity and the rate capability of the TDC readout system. This project is supported by BMBF and EU FP7.
        Speaker: Mr Maximilian Buechele (Physikalisches Institut der Albert-Ludwigs-Universitaet Freiburg)
        Slides
      • 4:00 PM
        A PowerPC-based control system for the ReadOut Driver module of the ATLAS IBL. 2h 30m
        he ATLAS experiment at LHC planned to upgrade the existing Pixel Detector with the insertion of an innermost silicon layer, called Insertable B-layer (IBL).A new front-end ASIC has been foreseen (named FE-I4) and it will be readout with improved off-detector electronics. In particular, the new Read-Out Driver module (ROD) is a VME-based board designed to process a four-fold data throughput. Moreover, the ROD hosts the electronics devoted to control operations whose main tasks are: providing setup busses to access configuration registers on several FPGAs, receiving configuration data from external PC, managing triggers and running calibration procedures. In parallel with a back-compatible solution with a DSP, a new ROD control circuitry with a PowerPC embedded into a FPGA has been implemented. In this paper the status of the PowerPC-based control system will be outlined, with major focus on firmware and software development strategies
        Speaker: Dr Riccardo Travaglini (INFN-Bologna)
        Paper
        Poster
      • 4:00 PM
        A prototype for the upgraded read out electronics of TileCal 2h 30m
        Upgrade plans for ATLAS hadronic calorimeter (TileCal) include full readout of all data to the counting room. We are developing a possible implementation of the future readout and trigger electronics aiming at a full functional demonstrator during Phase 0, starting from an existing functional test slice assembled using a combination of prototypes and emulators. Presently the first version of two PCBs in charge of digitization, control and communication are being developed. The design is highly redundant, using FPGAs with fault tolerant firmware for control and protocol conversion. Communication between on and off detector electronics is implemented via high speed optical links.
        Speaker: Mr Daniel Paer Erik Eriksson (Department of Physics-Stockholm University-Unknown)
        Paper
        Poster
      • 4:00 PM
        A radiation tolerant 5 Gb/s Laser Driver in 130 nm CMOS technology. 2h 30m
        The GigaBit Transceiver (GBT) project aims at the design of a radiation tolerant chip set for high speed optical data transmission. The chipset includes the GigaBit Laser Driver (GBLD), a radiation tolerant ASIC designed in a standard CMOS 130 nm technology. The GBLD is a laser driver designed to work to up to 5 Gb/s and capable to drive both VCSELs and some types of edge emitting lasers. The GBLD can provide a modulation current up to 24 mA and a bias current up to 43 mA with the pre-emphasis function to compensate for external capacitive load.
        Speaker: Giovanni Mazza (INFN sez. di Torino, Italy)
        Slides
      • 4:00 PM
        Advanced testing of the DEPFET minimatrix particle detector 2h 30m
        The DEPFET is an active pixel particle detector, in which a MOSFET is integrated in each pixel, providing first amplification stage of readout electronics. Excellent signal over noise performance is provided this way. The DEPFET sensor will be used as an inner pixel detector in the BELLE II experiment at electron-positron SuperKEKB collider in Japan. The DEPFET sensor requires switching and current readout circuits for its operation. These circuits have been designed as ASICs in several different versions, but they didn’t provide enough flexibility for precise detector testing. Therefore, a measuring system with a flexible control cycle range and minimal noise was designed for testing and characterization of small detector prototypes. Sensors with different design layouts and thicknesses are produced in order to evaluate and select the best performance for the Belle II application. Description of the test system as well as the first measurement results will be presented.
        Speaker: Jan Scheirich (Czech Technical University in Prague, Faculty of Electrical Engineering)
        Paper
        Poster
      • 4:00 PM
        AGET-SED : A 128-Channel Complete Data Acquisition system for solid state and gaseous detector 2h 30m
        To prepare future experiment, we need to qualify new solid state detectors and gaseous TPC. From T2K experiment and GET project, we develop a small board constituted of two 64 AGET asic, a 4-channel pipeline adc and a smart commercial board called “AVNET minimodule” to sequence the acquisition and send data in TCP/IP mode through the Ethernet network. The size of the board is 15 cm x 8 cm. Thanks to its small size, the board can be plugged close to the detector channels in vacuum or in gaseous environment. The paper presents the architecture of the system, performances and test result on micromegas readout plane, beam tracking detector and double sided stripped silicon detectors.
        Speaker: Mr Frédéric Druillole (CEA Saclay)
        Poster
      • 4:00 PM
        An Extended-Range Ethernet and Clock Distribution Circuit for Distributed Sensor Networks 2h 30m
        This talk describes a high speed ethernet-based data and clock network for applications which require an array of multiple sensor nodes distributed over distances of up to 250 m from a central hub. Speeds of up to 100 Mbit/sec and clock skew at the level of 50 ps are acheivable using commercially available network-grade twisted pair cables and low-power ethernet transceiver circuits. No fiber optic components are necessary. A specific application of this technology is presented: the ARA neutrino telescope located at the South Pole.
        Speaker: Dr Yifan Yang (Université Libre de Bruxelles)
        Paper
        Poster
      • 4:00 PM
        An FPGA based demonstrator for a topological processor in the future ATLAS L1-Calo trigger (``GOLD'') 2h 30m
        The existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based.\\ The LHC machine plans to bring the beam energy to the nominal value of 7 TeV and to increase the luminosity in the coming years. The current L1 trigger system is therefore seriously challenged.\\ To cope with the resulting higher event rate, as part of the ATLAS trigger upgrade, a new electronics module is foreseen to be added in the L1-Calo electronics chain: the topological processor.\\ Such processor is provided with fast optical I/O and large bandwidth capability, in order to use the information on the cluster position in space (i.e. jets in the calorimeters or muons in the muon detectors) and improve the purity of the L1 triggers streams by applying topological cuts within the latency budget.\\ In this talk, an overview of the adopted technological solutions and the R$\&$D activities on the demonstrator (``GOLD'') are presented.
        Speaker: Mr Andreas Ebling (J.G.U. Mainz)
        Paper
        Slides
      • 4:00 PM
        Architectural modeling of pixel readout chips Velopix and Timepix3 2h 30m
        We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout. In addition, Velopix must be immune to single-event upsets in its digital logic. The most important requirements for both of the chips are pixel size, timing resolution, low power and high-speed sparse readout. We describe the transaction level architectural models of the chips using SystemVerilog after which we refine these models to register-transfer level. The correctness of the models is ensured using Open Verification Methodology. We will also discuss the advantages gained from transaction level modelling.
        Speaker: Mr Tuomas Sakari Poikela (University of Turku / CERN)
        Paper
      • 4:00 PM
        AsAd, the Generic Electronics Front-End for Time Projection Chambers 2h 30m
        In experiments with radioactive beams from heavy ions facilities it is shown that active targets and TPCs experimental methods are effective means to study nuclear spectroscopy. The principle advantages are good resolution, versatility and high luminosity. To address the needs of the nuclear Physics community we are in the process of developing a Generic Electronic system for TPCs (GET) to cover small to medium sized instrumentation (64 to 32k channels)with a relatively wide charge dynamic ranges. The front-end electronics AsAd(ASIC Support & Analog-Digital conversion) sample input signals and transmits data to processing modules.
        Speaker: Jerôme Pibernat (CENBG/CNRS/IN2P3)
        Poster
      • 4:00 PM
        ASPIC: LSST camera readout chip 2h 30m
        The ASPIC chip has been designed to readout the 3.2Gpixels of the LSST camera focal plane. The dynamic range is more than 16 bit and the noise has to be less than 7µV rms with a crosstalk better than 0.05%. The architecture, chosen by LSST, is based on a “Correlated Double Sampling” with a “Dual Slope Integrator” method. Many modular tests benches have been developed to qualify this chip and perform its integration inside the CCD readout chain.
        Speaker: Mr David Pierre Martin (Lab. Phys. Nucl. Hautes Energies (LPNHE)-Univ. P. et Marie Curi)
        Paper
        Poster
        Slides
      • 4:00 PM
        Comparison of single event effect robustness of dual and triple well technologies at the 90 nm node 2h 30m
        As triple well technologies became available in recent years as an option for several submicron technologies, the question of their robustness against SEU with respect to single well versions has been asked, but a systematic comparison has been missing from the literature. This work present the first systematic comparison of the sensitivity to Single Event Upsets of latch cells designed in a 90nm CMOS and implemented in identical circuits realized in regular and isolated triple well technologies. Two types of CMOS latches were investigated: the first fabricated with NMOS transistors in a lightly doped p-well, while the second type, using identical layouts, was fabricated with isolated triple-well (deep buried n-well) NMOS transistors isolated from the p-substrate. The latter have shown a robustness increase to SEUs by a factor of 2 with respect to the former, albeit only at high LET of the ions. The impact on robustness of the voltage supply was also measured to be to about 20%. Finally, hits on the clock distribution network were observed corrupting the data stored in multiple cells.
        Speaker: Dr Sandro Bonacini (CERN)
        Paper
        Poster
      • 4:00 PM
        Conceptual Design of 3D Integrated Pixel Sensors for the Innermost Layer of the ILC Vertex Detector 2h 30m
        The paper presents a design of CMOS Pixel Sensor (CPS) using the vertical integration technology (3DIT), expected to alleviate the most essential limitations of 2D-CPS. Our objective is to develop an intelligent architecture in order to meet the requirements of the innermost layer of the International Linear Collider (ILC) vertex detector, which are particularly demanding in spatial resolution and associated readout speed. The sensor, with a pixel pitch of 23 µm, will be composed of 3-tiers Integrated Circuits (IC) with different functionalities: detection with in pixel analogue processing, pixel-level 3-bit Analogue to Digital Conversion (ADC) and fast parallelism sparse readout.
        Speaker: Mr FU Yunan (Institut Pluridisciplinaire Hubert Curien)
        Paper
      • 4:00 PM
        Conceptual design of a MGy tolerant integrated signal conditioning circuit in 130 nm CMOS 2h 30m
        The design of a radiation tolerant configurable discrete time signal conditioning circuit in 130nm CMOS technology for use with resistive sensors like strain gauge pressure sensors is presented. The circuit is intended to be used for remote handling in harsh environments in the International Experimental Thermonuclear fusion Reactor (ITER). The design features a 1.5V differential preamplifier using a Correlated Double Sampling (CDS) architecture at a sample rate of 20kHz. The gain is digitally controllable between 27 and 400. The nominal input referred noise voltage is only 12µV at room temperature. The circuit has a simulated radiation tolerance of more than 1MGy.
        Speakers: Mr Jens Verbeeck (K.U.Leuven) , Prof. Paul Leroux (K.U. Leuven)
        Paper
        Poster
      • 4:00 PM
        Cryogenic digital data links for a liquid argon time projection chamber 2h 30m
        In this paper we present the R&D towards cryogenic digital data links for a Liquid Argon Time Projection Chamber (LArTPC). An electrical data link with a commercial LVDS driver and a 20-meter CAT5E twisted pair can work up to 1 Gbps at liquid nitrogen temperature or 77 K. Components of a cryogenic optical data link, including a serializer ASIC, laser diodes, optical fibers, and optical connectors, have been test operating properly. Commercial Field Programmable Gate Arrays (FPGAs) continue to function properly at 77 K. A variety of commercial resistors and capacitors suitable to cryogenic operation have been identified.
        Speaker: Dr Tiankuan Liu (Southern Methodist University (US))
        Paper
        Slides
      • 4:00 PM
        DAQ systems for 10^8 channels detectors: design and system level simulations 2h 30m
        Calorimeters for a future International Linear Collider developed within the CALICE collaboration will feature about 10^8 channels. A scalable control and data acquisition system was developed. Is is based on GigaEthernet and a specific serial link packing slow control, fast control and read out data. Most of the hardware and firmware components are shared among the various detectors. The first prototype will be presented. Its extrapolation for a 10^8 channels detector requires stringent optimization studies about architecture and structural parameters. A first approach about specific tools for system level simulation based on SystemC and TLM technologies and their coupling to physics simulation and analysis environment will be presented.
        Speaker: Dr Remi Jean Noel Cornat (Laboratoire Leprince-Ringuet (LLR)-Ecole Polytechnique-Unknown)
        Poster
      • 4:00 PM
        DC-DC converters with reduced mass for trackers at the HL-LHC 2h 30m
        The development at CERN of low noise DC-DC converters for the powering of front-end systems enables the implementation of efficient powering schemes for the physics experiments at the HL-LHC. Recent tests made on the ATLAS short strip tracker modules confirm the full electromagnetic compatibility of the DC-DC converter prototypes with front-end detectors. The integration of the converters in the trackers front-ends needs to address also the material budget constraints. The impact of the DC-DC converters prototypes onto the ATLAS tracker modules material budget is discussed and mass reduction techniques are explored, leading to a compromise between the electromagnetic compatibility and mass. Low mass shield implementations and Aluminum core inductors are proposed. Also, the impact on emitted noise due to a size reduction of critical components is discussed. Finally, material reduction techniques are discussed at the board layout and manufacturing levels.
        Speaker: Georges Blanchot (CERN)
        Paper
        Poster
      • 4:00 PM
        Design and Development of Electronics for the EuXFEL Clock and Control System 2h 30m
        The development of the Clock and Control (CC) hardware and firmware for the EuXFEL DAQ system is presented. The system exploits the data handling advances provided by the new telecommunication architecture standard for physics. The CC is responsible for synchronising the DAQ system to overall system timing. The hardware consists of a DESY designed MTCA.4 board and a UCL designed Rear Transition Module (RTM). Each RTM controls up to 16 Front End Modules (FEMs) for a 1 Megapixel 2D detector. The CC system is designed to provide extendibility and scalability to support future upgrades to the DAQ or larger detectors.
        Speaker: Dr Erdem Motuk (University College London)
        Paper
        Poster
      • 4:00 PM
        Design of a "Digital Atlas Vme Electronics" ( DAVE ) Module 2h 30m
        ATLAS-SCT has developed a new ATLAS trigger card, 'Digital Atlas Vme Electronics' ("DAVE"). The unit was designed to provide a versatile array of interface and logic resources, including a large FPGA. It interfaces to both VME bus and USB hosts. DAVE aims to provide exact ATLAS CTP functionality, with random trigger, simple and complex deadtime, ECR, BCR etc. being generated to give exactly the same conditions in standalone running as experienced in combined runs. DAVE provides additional hardware and a large amount of free firmware resource to allow users to add or change functionality.
        Speaker: Mr Martin Postranecky (Department of Physics and Astronomy, University College London)
        Paper
        Poster
        Slides
      • 4:00 PM
        Design of the Train Builder Data Acquisition System for the European-XFEL 2h 30m
        The Train Builder is an Advanced Telecom ATCA based custom data acquisition system designed to provide a common readout system for the large 2D Mega-pixel detectors presently under construction for the European-XFEL facility in Hamburg. Each detector outputs 10 GBytes/sec of raw data over multiple 10 Gbps SFP+ optical links. The Train Builder DAQ system will merge detector link image fragments from up to 512 X-ray pulses in each XFEL bunch train and send the complete detector “movies” of images to a farm of PCs. The Train Builder data links will operate with 10G IP based protocols implemented in FPGA logic.
        Speaker: John Coughlan (STFC Rutherford Appleton Laboratory)
        Paper
        Poster
      • 4:00 PM
        Development and validation of a 64 channel front end ASIC for 3D directional detection with MIMAC 2h 30m
        A front end ASIC has been designed to equip the µTPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the “Time Over Threshold” information for each of those. This 64 digital information, sampled at a rate of 50 MHz, can be transferred at 400 MHz by 8 LVDS serial links. Additionally, the energy is measured by groups of 16 channels and is delivered in two different analogue gains. Eight ASIC were validated on a 2x256 strips of pixels prototype.
        Speaker: Olivier Raymond Bourrion (Laboratoire de Physique Subatomique et de Cosmologie (LPSC)-Univ)
        Paper
        Poster
      • 4:00 PM
        Development of DC/DC converter in VHF band 2h 30m
        We will present some new ideas on the design of different parts of DC/DC converter which operates on Very High Frequency. I show different topologies, and its power efficiency influence, which is being achieved during design stage of 2 years project called Brahms. There are recent interesting results, but not final solution yet. The presentation is focused to the perspective of power conversion in hundred Megahertz operational range. The reason to move up operating frequency of DC/DC converter over the bandwidth of detector front-end is to reduce interference.
        Speaker: Ivo Polak (Institute of Physics)
        Poster
      • 4:00 PM
        Development of Low--Power Small--Area L--2L CMOS DACs for Multichannel Readout Systems 2h 30m
        The design and measurements of 8--bits DACs based on L--2L ladder architecture are presented. The main design goals were low power consumption and low area. Such features allow using the DAC for channel parameter trimming in multichannel readout system. The PMOS and NMOS based DACs are studied in wide range of biasing conditions and for two operation modes -- as current generator and current divider. The prototypes of 0.034 mm$\mathrm{^2} $ area are fabricated in 0.35$\mathrm{\mu} $m CMOS technology. The measurements show that the maximum INL and DNL are both below 0.5 LSB. The power consumption is about $\mathrm{80 \mu W} $.
        Speaker: Mr Dominik Przyborowski (AGH University of Science and Technology)
      • 4:00 PM
        Developments at the UC Davis Facility for Interconnect Technologies 2h 30m
        As silicon detectors in HEP require increasingly complex assembly procedures, the availability of a wide variety of interconnect technologies provides more options for overcoming obstacles in generic R&D. I present recent progress and challenges faced in various interconnect technologies: gold stud and double gold stud bonding, deposition and bonding of indium bumps, solder ball bonding and dispensing and bonding using conductive epoxy. Advantages and limitations of each technique are analyzed to provide insight into potential applications for each method. Optimization of procedures and ideal parameters for each technique, developed at the UC Davis Facility for Interconnect Technology, are presented.
        Speaker: Christian Neher (University of California at Davis)
        Paper
      • 4:00 PM
        Double-sided silicon strip modules for the ATLAS tracker upgrade in the High-Luminosity LHC collider 2h 30m
        The Large Hadron Collider (LHC) will extend its current physics programme by increasing the peak luminosity by one order of magnitude. For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker. The super-module programme is an integration concept for the barrel short-strip region of the future ATLAS tracker in which double-sided silicon micro-strip modules are assembled into a local support structure. Results from first module prototypes will be reported. The electrical performance of several modules integrated together into a common structure will be shown.
        Speaker: Sergio Gonzalez Sevilla (DPNC, University of Geneva)
        Paper
        Poster
      • 4:00 PM
        Efficient Signal Contitioning by an FIR Filter for Analog Signal Transmission over Long Lines 2h 30m
        In the Belle II SVD readout chain the analog singnals will be transmitted over long lines. This leads to signal distortion, caused by the frequency dependent transfer function of the cable and also by reflections, which occour whenever the line impedance changes. One possibility to compensate these effects is a dedicated filter at the receiver end. This presentation describes the approach to realize the required filter as a finite impulse response (FIR) filter. We further show how such a filter can be implemented in the firmware of an FPGA and the required FIR coeffients can directly be calculated from the output signal of the APV25 front-end chip.
        Speaker: Mr Christian Irmler (HEPHY Vienna)
        Paper
        Poster
      • 4:00 PM
        Evaluation of Emerging Parallel Optical Link Technology for High Energy Physics 2h 30m
        Modern particle detectors utilize optical fiber links to deliver event data to upstream trigger and data processing systems. Future detector systems can benefit from the development of dense arrangements of high speed optical links emerging from industry advancements in transceiver technology. Supporting data transfers of up to 120 Gbps in each direction, optical engines permit assembly of the optical transceivers in close proximity to ASICs and FPGAs. Test results of some of these parallel components will be presented including the development of pluggable FPGA Mezzanine Cards equipped with optical engines to provide to collaborators on the Versatile Link Common Project for the HI-LHC at CERN.
        Speaker: Mr Alan Prosser (Fermilab)
        Paper
        Slides
      • 4:00 PM
        FATALIC, a wide dynamic range integrated circuit for the tilecal VFE Atlas upgrade 2h 30m
        The ATLAS upgrade will require more efficient electronics to fulfil the new performances expected by the experiment. Concerning the readout electronics of the Tile Calorimeter, the replacement of the 3in1 board by an integrated circuit is under study. The proposed circuit is composed of a multi-gain current conveyor, followed by shapers, an integrator for the calibration and an analog-to-digital converter. This solution presents better performances, concerning the noise, and the power consumption. Two prototype chips have been submitted using the IBM 130nm CMOS technology: one with a three gains current conveyor, another with an enhanced current conveyor associated with shapers.
        Speaker: Dr Nicolas Pillet (Lab. de Physique Corpusculaire (LPC))
        Poster
      • 4:00 PM
        First measurements of single event upsets in the readout control FPGA of the ALICE TPC detector 2h 30m
        In the main tracking detector of ALICE, the Time Projection Chamber (TPC), an SRAM based FPGA from Xilinx is implemented in the Readout Control Unit (RCU)of the front-end electronics and controls the read out of data from the detector. This paper will present the first measurements of single event upsets in this FPGA. The results will be compared to previous simulations and discussed in light of the expected integrated luminosity.
        Speaker: Dr Ketil Røed (CERN)
        Paper
        Poster
      • 4:00 PM
        Flexible system of the CMS ECAL OD electronics firmware update 2h 30m
        This poster describes the implementation of a flexible system for the electromagnetic calorimeter (ECAL) Off Detector (OD) electronics firmware update and the corresponding software tools designed to manage the update operation. The idea is to equip each ECAL VME64x crate with the new JTAG Distribution Board (JDB) that access XILINX and ALTERA FPGAs JTAG chains for trigger (TCC68/48) and data acquisition (DCC) boards. This solution allows:  Improve access flexibility and reduce the time needed to reprogram TCCs and DCCs firmware.  Increase mechanical safety, excluding any touching of the fragile fibers connected to OD electronics every time the update is perfomed;  Perform the firmware update via remote (VME-MTM) mode. New FPGAs programming code can be loaded to the OD electronics FPGAs through the specific Programming Cable from a dedicated PC connected to JDB or from VME-MTM bus. On the JDB there are three modes to select the JTAG path: First, manually, via a ten position switch placed on the front-panel. Second, from a PC through USB port. Third, the VME/JTAG interface implemented on a FPGA. The system has been installed in CMS counting room (USC55) and used for the firmware upgrades of the CMS electromagnetic calorimeter data acquisition and trigger system electronics.
        Speaker: Jose Carlos Rasteiro Da Silva (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)
        Paper
        Slides
      • 4:00 PM
        GEM400: A Front-End Readout chip based on Capacitor Switch Array for Pixel-based GEM Detector 2h 30m
        The upgrade of Beijing Synchrotron Radiation Facility(BSRF) need two-dimensional position-sensitive detection equipment to improve the experimental performance. New structures and new technology GEM detector, in particular, pixel-based(Pad) GEM detector, has good prospects in the domain of synchrotron radiation and high energy physics experiments for its simple structure, superior performance and the flexible way of read-out. For the read-out of pixel-based GEM detector, we proposed a new read-out program, designed read-out ASICs based on capacitor switch array, and achived the read-out of pixel-based GEM detector using System in Package technology.
        Speaker: Dr Huaishen LI (IHEP, C.A.S.)
        Paper
        Poster
      • 4:00 PM
        GOSSIPO-4: an array of high resolution TDCs with a PLL control 2h 30m
        GOSSIPO-4 is a prototype chip featuring an array of high resolution Time to Digital Converters (TDC) with a PLL control that will be taped out on the 9th of August 2011. This prototype is the successor of GOSSIPO-3 test chip and the precursor of the 65k pixel TimePix3 chip. The prototype is being developed to test a set of new features that will be used in TimePix3, including a 8 pixel structure sharing one fast oscillator with a new topology, a PLL to provide the control voltage to the oscillators, a custom fast counter and a new small-area cell library.
        Speaker: Mr Francesco Zappon (Nikhef)
        Paper
      • 4:00 PM
        Initial tests of CMS Binary Chip with Sensor 2h 30m
        Initial tests the CBC binary readout chip connected to a sensor are presented.
        Speaker: Dr David Cussans (University of Bristol)
        Paper
        Poster
      • 4:00 PM
        Irradiation of DEPFET-like transistors with CO-60 gamma source up to 10 MRad 2h 30m
        The Pixel Detector (PXD) of the Belle II experiment at superKEKB accelerator in Japan is based in the DEPFET technology. Two layers of 8+12 modules at a radius of 13 and 22 mm will give a spatial resolution below 10 µm. The radiation level expected in the first layer in ten years of operation is about 10 MRad of total ionizing dose. In order to study the tolerance of the DEPFET technology sixty devices were irradiated using a standard procedure like 60Co gamma source. Different doping types, channel sizes and biasing conditions were studied.
        Speaker: Dr Pablo Vazquez Regueiro (University of Santiago de Compostela, IGFAE)
        Poster
      • 4:00 PM
        KLauS - A Charge Readout and Fast Discrimination Chip for Silicon Photomultipliers (SiPMs) 2h 30m
        KLauS is an ASIC in AMS 350nm Bicmos Technology with 12 Silicion Photomultiplier (SiPM) readout channels. It is designed to be used in the plastic sintillator based Analog Hadron Calorimeter (AHCal) at a future Linear Collider. Its dynamic range reaches 200pC and SNR is better than 10 for single photon signal of very low gain SiPMs. The chip provides 2V bias tuning to compensate SiPM breakdown voltage variations. The measured timing jitter is 50ps for nominal AHCal MIP response (15 pixels fired). Power pulsing option has been implemented such that one can make use of ILC bunch crossing clock structure. The total power is 25uW.
        Speaker: Mr Tobias Harion (Kirchhoff Institute for Physics)
        Paper
        Poster
      • 4:00 PM
        Low mass aluminium microstrips for data transmission in the Micro Vertex Detector of the Panda experiment. 2h 30m
        The Micro Vertex Detector is the innermost part of the Panda experiment and is constituted of pixels and strips. The design foresees a triggerless data acquisition, and Topix is the current Asic solution for the pixel readout featuring more than 10k cells with a serial data output exploiting the GigaBit Transceiver project, at present under development at CERN, that will manage the data transmission and the clock distribution. The connections on the sensor module are made in aluminium to keep low the impact on the material budget; the first prototypes were produced with a 1m length and folded layout, while the width was in the range 100÷200µm. At present there are samples with the same extent but a straight layout to evaluate the aluminium uniformity, and electrical tests are ongoing to verify the behaviour with transceivers complying with the Scalable Low Voltage Signaling standard.
        Speaker: Paolo De Remigis (INFN)
        Paper
        Slides
      • 4:00 PM
        Low Noise Preamplifier ASIC for the PANDA - Experiment 2h 30m
        For the electromagnetic calorimeter of the PANDA - Experiment the ASIC – Design – Group of the GSI – Experiment – Electronics department developed an integrated preamplifier and shaper ASIC. The chip developed for spectroscopy using is optimized for the readout of large area avalanche photo diodes (LAAPD) with a capacitance of 280 pF and an event rate of 350 kHz. Each ASIC has two equivalent analog channels consisting of a charge sensitive amplifier, a third order shaper stage and differential output drivers. The on chip implemented programmable voltage references are chosen to compensate the temperature dependancy on the output DC and ensure the full dynamic range.
        Speaker: Dr Peter Wieczorek (GSI Darmstadt, Germany)
        Paper
        Poster
      • 4:00 PM
        MICROROC: MICROMEsh GAseous Structure Read-Out Chip 2h 30m
        MICRO MEsh GAseous Structure (MICROMEGAS) and Gas Electron Multipliers (GEM) detectors are two candidates for the active part of a Digital Hadronic CALorimeter (DHCAL) as part of a high energy physics experiment at the International Linear Collider. Physics requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital calorimeter). To validate the concept of digital hadronic calorimetry, a cubic meter technological prototype, made of 40 planes of one square meter each, is compulsory. Such a technological prototype involves not less than 400 000 electronic channels, thus requiring the development of front-end ASIC. Based on the experience of previous ASICs (DIRAC and HARDROC) and on multiple testbeam results, a new ASIC, called MICROROC for MICRO mesh GAseous Structure Read-Out Chip, has been recently developed at IN2P3 jointly by OMEGA/LAL and LAPP microelectronics groups. It was submitted to foundry in June 2010, and prototypes were delivered at the beginning of September, a low volume production has been tested in 2011 and the detector testbeams are scheduled in summer 2011.
        Speaker: Mrs Nathalie Seguin-Moreau (LAL)
        Paper
        Poster
      • 4:00 PM
        MicroTCA-based Global Trigger Upgrade project for the CMS experiment at LHC 2h 30m
        At LHC 40 million collisions of proton bunches occur every second, resulting in about 800 million proton collisions. The Level-1 trigger, a custom designed electronics system based on FPGA technology and the VMEbus system, performs a quick on-line analysis of each collision every 25 ns and decides whether to reject or to accept it for further analysis. As part of the Global Trigger Upgrade, the current system will be redesigned and implemented for MicroTCA based technology, which allows engineers to detect all possible faults on plug-in boards, in the power supply and in the cooling system. Additionally, reconfigurability and testability will be supported based on the next system generation.
        Speaker: Dr Babak Rahbaran (HEPHY Vienna--Institute of High Energy Physics Vienna)
        Paper
        Poster
      • 4:00 PM
        Modelling radiation-effects and annealing in semiconductor lasers for use in future particle physics experiments 2h 30m
        Optical link components used in future particle physics experiments will typically be exposed to intense radiation fields during the lifetime of the experiment and the qualification of these components in terms of radiation tolerance is thus required. We have created a model that describes the degradation of the L-I characteristic of a semiconductor LASER undergoing irradiation with the annealing processes taken into account. This model can be used to predict the behaviour of a laser being irradiated with the different particle fluxes at different locations inside a particle physics experiment. The robustness of the model has been checked against the experimental data obtained during high-fluence (in excess of 10^15 particles/cm^2) neutron and pion irradiation testing in 2009 and 2010.
        Speaker: Mr Pavel Stejskal (CERN)
        Paper
      • 4:00 PM
        Novel interconnect techniques for hybrid pixel detectors 2h 30m
        The next generation hybrid pixel detectors in particle physics experiments require reduced mass budget, increased interconnection density and they need to be tileable to seamlessly cover large areas. These criteria cannot be fulfilled with present day interconnection techniques. As a result the particle physics community has recently put in a lot of effort to investigate and evaluate variety of novel interconnection technologies. This paper presents results of interconnect studies done at CERN PH/ESE, focusing mainly on two technologies: Carbon Nano Fiber (CNF) interconnects and Through Silicon Vias (TSV). Initial results of the CNF interconnects are reviewed and the status and future plans of a joint TSV development project with CEA-LETI Minatec are presented.
        Speaker: Timo Tick (CERN)
        Paper
        Poster
      • 4:00 PM
        Open Hardware for CERN’s Accelerator Control Systems 2h 30m
        The accelerator control systems at CERN will be renovated and many electronics modules like analog and digital I/O, level converters and repeaters, serial links and timing modules are being redesigned. The new developments are based on VITA and PCI-SIG standards such as FMC, PCI Express and VME64x. The Wishbone specification is used as SOC bus. To attract partners, the projects are developed in an ‘Open’ fashion. Within this Open Hardware project new ways of working with industry are being tested and it will be shown that industry can be involved at all stages, from design to production and support.
        Speaker: Mr Erik van der Bij (CERN)
        Paper
        Poster
      • 4:00 PM
        Power Converters for Future LHC Experiments 2h 30m
        The paper describes power switching converters suitable for possible power supply distribution networks for the upgraded detectors at the High Luminosity LHC collider. The proposed topologies have been selected by considering their tolerance to the highly hostile environment where the converters will operate as well as their limited electromagnetic noise emission. The analysis focuses on the description of the power supplies for noble liquid calorimeters, such as the Atlas LAr calorimeters, though several outcomes of this research can be applied to other detectors of the future LHC experiments. Experimental results carried on demonstrators are provided.
        Speaker: M. Citterio (INFN Milano)
        Paper
        Poster
      • 4:00 PM
        Power Network impedance effects on noise emission of DC-DC converters 2h 30m
        The characterization of electromagnetic noise of DC-DC converters is a critical issue that has been analyzed during the design phase of CMS tracker upgrade. Previous simulation studies showed important variations of conducted emission of DC-DC converters among impedances and power network topologies. Several tests have been performed on real DC-DC converters to validate the Pspice model and simulation results. This paper presents these test results. Conducted and radiated noise emissions at the input and at the output form DC-DC converters have been measured for different types of power network and FEE impedances. Special attention has been paid to the influence of carbon fiber in the CM noise emissions. The results of these studies show important recommendations and criteria to be applied to integrate the DC-DC converters to decrease the system noise level.
        Speaker: Maria Cristina Esteban Lallana (Instituto Tecnologico de Aragon)
        Paper
        Poster
      • 4:00 PM
        Power Supply and Pulsing Strategies for the International and Compact Linear Colliders 2h 30m
        We discuss the power supply and distribution for new linear accelerators in particular with respect to the innovative architecture of the pulsing mode. The possibility to exploit the small duty-cycle becomes a critical factor to optimize the peak and mean power over the connections and cabling to reduce the loss, undesidered heating generation and interference and other sources of noise. We investigate on how to organize a possible power distribution to assure a stable supply with limited space like in the vertex detectors and give some examples of implementation
        Speaker: Andrea Brogna (Karlsruher Institut für Technologie, Institut für Prozessdatenverarbeitung und Elektronik)
        Paper
      • 4:00 PM
        Prototype Pixel Optohybrid for the CMS phase 1 upgraded Pixel Detector 2h 30m
        The CMS Pixel detector phase 1 upgrade calls for an optical readout system operating digitally at or above 320 Mb/s. Since the re-use of the existing link components as installed is excluded, we have designed a new Pixel Optohybrid (POH) for use within this system. We report on the design and choice of components as well as their measured performance. In particular, we have studied the impact upon error-free link operation of the way the data are encoded before being transmitted over the link. We have thus demonstrated the feasibility of operating the new POH within the upgraded readout system.
        Speaker: Dr Jan Troska (CERN PH/ESE)
        Paper
        Poster
      • 4:00 PM
        Recent progress in the development of 3D deep n-well CMOS MAPS 2h 30m
        In a DNW MAPS a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. Various solutions complying with different sensor layout and pixel pitch have been fabricated in a planar (2D) 130nm CMOS technology. This work will discuss the design and characterization of deep N-well (DNW) monolithic active pixel sensors (MAPS) fabricated in a vertical integration (3D) CMOS technology. 3D CMOS technology could be very effective in overcoming typical limitations of monolithic active pixel sensors. The final paper will discuss the features of the front-end electronics with the first experimental results from the test of 3D DNW MAPS.
        Speaker: Gianluca Traversi (University of Bergamo and INFN Pavia)
        Paper
        Poster
      • 4:00 PM
        Redesign of the Back of Crate Card (BOC) for the ATLAS IBL 2h 30m
        The pixel detector of the ATLAS experiment at CERN will be upgraded with an additional layer (IBL) in 2013. To handle the data readout the currently used VME card pairs consisting of a back of crate card (BOC) and a read out driver (ROD) are being redesigned. We present details of the hardware design of the new BOC prototype. It takes advantage from modern FPGA technology and commercial optical modules and abandons the need for a variety of custom components used on the old card. Also the throughput is four times higher and additional features are implemented.
        Speaker: Mr Nicolai Schroer (ZITI, LS Informatik V, Heidelberg University, Mannheim)
        Paper
        Poster
      • 4:00 PM
        Reducing pixel-to-pixel disparities in Geiger mode avalanche photodiodes by using gated operation 2h 30m
        The gated operation is proposed as an effective method to reduce and uniformize noise figures in particle tracking pixel detectors based on Geiger mode avalanche photodiodes for future linear colliders. A protoype based on a 3x3 array with the sensor and the front-end electronics monolithically integrated has been fabricated with the conventional HV-AMS 0.35µm technology. Experimental results demonstrate the reduction of pixel-to-pixel variations by applying this technique.
        Speaker: Ms Eva Vilella (University of Barcelona)
        Paper
        Poster
      • 4:00 PM
        Remote Access to Xilinx Programmable Devices in the CSC Endcap Muon Electronic System at CMS 2h 30m
        We present the status of hardware and software tools for remote access to Xilinx programmable devices in the Cathode Strip Chamber Endcap Muon Electronic System at the CMS experiment at CERN.
        Speaker: Mikhail Matveev (Rice University)
        Paper
      • 4:00 PM
        Single-Event Upset testing of the Versatile Transceiver 2h 30m
        The Versatile Transceiver will be deployed on detectors that will be operated at the upgraded HL-LHC where the instantaneous luminosity will be increased by a factor of 5-10 with respect to the nominal LHC. All components housed at the front-ends must thus be immune to single-event upsets to a level compatible with the correct operation of the detector systems. We will carry out an irradiation test to validate correct operation and the results will be reported in this paper.
        Speaker: Dr Jan Troska (CERN PH/ESE)
        Paper
        Poster
      • 4:00 PM
        SPACIROC: A Front-End Readout ASIC for the JEM-EUSO observatory 2h 30m
        The SPACIROC ASIC is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). The main goal of JEM-EUSO is to observe Extensive Air Shower (EAS) produced in the atmosphere by the passage of the high energetic extraterrestrial particles above a few 10^19 eV. A low-power, rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which are going to equip the detection surface of JEM-EUSO. Two main features of this ASIC are the photon counting mode for each input and the charge-to-time (Q-to-T) conversion for the multiplexed channels. In the photon counting mode, the 100% triggering efficiency is achieved for 50fC input charges. For the Q-to-T converter, the ASIC requires a minimum input of 2pC. In order to comply with the strict power budget available from the ISS, the ASIC is needed to dissipate less than 1mW/channel. The design of SPACIROC and the test results are presented in this paper. SPACIROC is a result of the collaboration between OMEGA/LAL-Orsay, France, RIKEN, ISAS/JAXA and Konan University, Japan on behalf of the JEM-EUSO consortium.
        Speaker: Gisele Martin-Chassard (Unknown)
      • 4:00 PM
        Studies for the detector control system of the new ATLAS Pixel detector 2h 30m
        In the context of the LHC upgrade to the HL-LHC the inner detector of the ATLAS experiment will be replaced completely. As part of this redesign there will also be an new pixel detector. This new pixel detector requires a control system which meets the strict space requirements for electronics in the ATLAS experiment. To accomplish this goal we propose a DCS (Detector Control System) network with the smallest form factor currently available. This network consists of a DCS chip located in close proximity to the interaction point and a DCS controller located in the outer regions of the ATLAS detector. These two types of chips form a star shaped network with several DCS chips being controlled by one DCS controller. Both chips are manufactured in deep sub-micron technology. We present prototypes with emphasis on studies concerning single event upsets.
        Speaker: Mr Lukas Püllen (Bergische Universitaet Wuppertal)
        Paper
        Poster
      • 4:00 PM
        TEL62: an integrated trigger and data acquisition board 2h 30m
        The main goal of the NA62 experiment at the CERN SPS is to measure the branching ratio of the K+ → π+νν decay, collecting about 100 events in two years of data taking. The nature of the experiment puts stringent requirements on the trigger and data acquisition system: the efficient online selection of interesting events and loss-less readout at high rate will be key issues. Readout uniformity among different sub-detectors and scalability were taken into account in the architecture design. For this purpose an integrated trigger and data acquisition board (TEL62) has been designed and the first prototype is currently under test.
        Speakers: Dr Elena Pedreschi (Sezione di Pisa (INFN)) , Dr Franco Spinella (Sezione di Pisa (INFN))
        Paper
      • 4:00 PM
        Tests of ATLAS SCT Front-end Amplifier's ASIC Susceptibility to Beam Loss Scenario 2h 30m
        The Semi-Conductor Tracker in the ATLAS experiment at the Large Hadron Collider is potentially subject to various beam loss scenarios. It is important to understand what the effect of such an event would be on the operation of the SCT detector. Previous tests have shown the ABCD ASIC to be the weak point of the SCT modules when exposed to the intense radiation of a beam loss incident. According to the system specification, ABCD is expected to survive a 5nC charge over 25ns. In this study, we validate the 5nC threshold and test the ABCD's survival at greater charge dosages.
        Speaker: Dr Alexander Grillo (UCSC)
        Paper
        Poster
      • 4:00 PM
        The Data Handling Processor (DHP) for the DEPFET Pixel Vertex Detector at BelleII 2h 30m
        A major upgrade of the current Japanese B-Factory (KEK-B) is planned by the fall of 2013. Together with this new machine (SuperKEK-B), also a new detector, BelleII, will be operated to fully exploit the higher luminosity (40 times larger than the previous experiment). One of the major changes in the new experiment will be the introduction of a new sub-detector, close to the interaction point, to allow a precise reconstruction of the decay vertices of the B meson systems. This pixel detector, based on the DEPFET technology, will consist of 20 ladder modules arranged in two cylindrical layers around the beam pipe. Each of the modules will be read-out independently by a combination of analog and digital ASICs placed at both ends of each sensor. The digital chip, the Data Handling Processor (DHP), is designed to control the readout chain and to pre-process and compress the data. The chip structure and the latest results will be presented.
        Speaker: Mr Mikhail Lemarenko (Physikalisches Institut-Universitaet Bonn)
        Paper
        Poster
      • 4:00 PM
        The Front-End Concentrator card for the RD51 Scalable Readout System 2h 30m
        The Scalable Readout System (SRS) was developed within RD51 collaboration as a multi-channel readout system, allowing ASICs, hybrids or discrete frontends with analog, binary or digital readout over a customizable link interface. User-specific frontends are linked to adapter cards which are straddle-mounted to Front-end Concentrator cards (FEC). The ensemble (Adapter + FEC card) forms a 6Ux220 mm unit. The most common adapter card is a 16-channel ADC card for analogue frontends like the APV25 or Beetle-based hybrids. More adapter cards for digital or more specific applications are existing or under design. Dozens of other applications are starting and a fast growing community of users and developers is working on SRS hardware, firmware and software.
        Speakers: Dr Hans Muller (CERN) , Dr José Francisco Toledo Alarcón (Valencia Polytechnic University)
        Paper
      • 4:00 PM
        The MEMDYN chip: a new circular memory prototype for a plannar pixel sensors readout IC 2h 30m
        A low-power and low-area circular memory has been designed in a 130 nm technology. This prototype aims to be integrated into a plannar pixel sensors readout 3D integrated circuit for the future ATLAS high luminosity upgrade. Three types of memory cell have been designed: one with Typical transistors, an other with low-Vt transistors and the last one with custom enclosed transistors. The digital data is stored in parasitic capacitance between the gate and the source of a NMOS transistor. Functionality and performance, before and after irradiation, will be shown.
        Speaker: Mr Damien Thienpont (IN2P3/LAL)
        Poster
      • 4:00 PM
        The NA62 Liquid Krypton Calorimeter Readout Module 2h 30m
        The NA62 experiment will be focused on precision tests of the Standard Model via studies of ultra-rare decays of the charged kaons. The high resolution Liquid Krypton (LKr) calorimeter of the NA48 experiment will provide a photon-veto with hermetic coverage from zero out to large angles from the decay region. The study of an upgraded readout system began in 2008. This paper presents the Calorimeter REAdout Module (CREAM), an upgrade project for the backend part of the LKr data acquisition chain. The CREAMs will provide 40 MHz sampling of 13248 calorimeter channels, data buffering during the SPS spill, zero suppression, and programmable trigger sums for the experiment trigger processor.
        Speaker: Vladimir Ryjov (CERN)
        Paper
        Poster
      • 4:00 PM
        The Nectar GHz Digitizer ASIC for the Cherenkov Telescope Array 2h 30m
        The future international high energy gamma ray observatory, the Cherenkov telescope Array (CTA), will consist in an array of 50-100 dishes of various sizes and various spacing, each equipped with a camera, made of few thousands fast photodetectors and its associated front-end electronics. The total number of electronics channels will be larger than 100,000 to be compared to the total of 6,000 channels of the 5-telecopes H.E.S.S. array. To optimize the overall CTA cost, a consequent effort is done to lower the cost of the electronics while keeping performances at less as good as the one demonstrated on the current experiments and simplifying its maintenance. This will be allowed by mass production, taking benefit of the use of standardized modules and massive integration of front-end functions in ASICs. In the framework of the NECTAR program, supported by the French ANR, a new detection module, housing the photodetectors, their high voltage power supplies and the associated front-end electronics has been studied. As in the H.ES.S. camera, the front-end electronics architecture is based on the very early digitization at rate higher than the GHz of the photodetector signals performed by a wide dynamic range analogue memory ASIC. A new digitizer chip, called NECTAR0, integrating a 2-channel, 1024-cell depth, high speed analogue memory together with a 12-bit, 20MS/s ADC followed by a 240Mbit/s digital serializer. Its targeted performances (11.6 bit dynamic range, 3.2 GS/s maximum frequency, power consumption) are equivalent or better than the one of the previous generation of chips used in H.E.S.S. 2. . The paper describes both the architecture of this new chip and reports its measured performances within a realistic environment.
        Speaker: Dr David Gascon (Universidad de Barcelona)
        Poster
      • 4:00 PM
        The New HADES Trigger and Data Acquisition System 2h 30m
        The data transport and trigger system of the HADES di-electron spectrometer operating at GSI, Germany was upgraded recently. The main goal was to substantially increase the event rate capabilities to reach trigger rates of up to 100 kHz and data rates of 400 MByte/s. The whole data communication system is based on FPGA-equipped platforms connected by optical links. Here, a custom network protocol, TrbNet, provides a framework to transport triggers, data and control information over the same physical network. In collaboration with groups from experiments of the FAIR accelerator complex, further developments based on the versatile hardware and communication protocol are being pursued.
        Speaker: Mr Jan Michel (Goethe University Frankfurt)
        Paper
        Poster
      • 4:00 PM
        The readout electronics for the hybrid avalanche photon detector 2h 30m
        We are developing the readout electronics for the proximity focusing hybrid avalanche photon detector (HAPD), the baseline photon sensor of the Belle II aerogel RICH. The detector, positioned in the spectrometer forward direction inside the 1.5 T magnetic field, has to efficiently detect the single photons. The readout electronics has to digitize small analog signals and transfer them to the central acquisition system of the experiment. Due to a very limited available space behind the HAPD it has to consume low power. The design, on the bench tests of the readout board prototypes will be presented and their functionality compared with the simulation.
        Speaker: Mr Andrej Seljak (IJS Institute Ljubljana)
        Paper
        Poster
      • 4:00 PM
        The Readout Electronics of the NA62 Large Angle Photon Veto System 2h 30m
        The branching ratio for the decay K+ -> pi+ nu anti-nu is sensitive to new physics; the NA62 experiment will measure it to within about 10%. To reject the dominant background from channels with final state photons, the large-angle vetoes (LAVs) must detect particles with 1-ns time resolution and 10% energy resolution over a very large energy range. Our custom readout board uses a time-over-threshold discriminator as a straightforward solution to satisfy these criteria. A prototype of the readout system was extensively tested together with a LAV module at CERN in summer 2010.
        Speaker: Dr Mauro Raggi (Laboratori Nazionali di Frascati (LNF)-Istituto Nazionale Fisic)
        Paper
        Poster
      • 4:00 PM
        Thermal performance of carbon foams used as heat sink for the MVD-Panda. 2h 30m
        The Micro Vertex Detector (the MVD) for the Panda experiment is optimized for the detection of the secondary vertices and for maximum acceptance close to the interaction point. The experimental set-up requires sophisticated solutions for the detector integration in order to maintain a stringent material budget. The thermal power produced by the “on board” read-out electronics is fast removed using carbon foam as heat sink. Two types of carbon foam are under evaluation. Both, the mechanical and thermal properties behaviour under radiating field are studied. Results from finite element thermal analyses and test bench are also presented.
        Speaker: Dr Giuseppe Giraudo (INFN-Torino)
        Paper
        Poster
      • 4:00 PM
        Timing Distribution for the Belle II Data Acquistion System 2h 30m
        At Belle II, most of the digitization is made inside or near the detector, and the digitized data are collected via high-speed optical serial links. Each of the frontend electronics boards equips at least one FPGA for a unified data link implementation, and at the same time to receive a system clock, the level-1 trigger and other fast timing signals and provide fast status signals. These timing signals are serialized and delivered via a commodity category-7 LAN cable, through a distribution network of cascaded 1-to-20 distribution modules. We report the initial performance test results of this timing distribution system.
        Speaker: Mikihiko Nakao (KEK)
        Paper
      • 4:00 PM
        Trigger-less readout electronics for the PANDA Electromagnetic Calorimeter 2h 30m
        The PANDA collaboration at the future FAIR facility at Darmstadt, Germany, will employ antiproton annihilations to investigate yet undiscovered charm-mesons and glueballs. The rich physics program requires various sophisticated event-selection criteria based e.g. on invariant mass, secondary vertices, and time correlations. Therefore, the readout electronics is designed such that all detectors may contribute to the event-selection process. The front-end electronics has built-in intelligence to extract and transmit only physically relevant information. A prototype of the corresponding readout chain was built for the PANDA Electromagnetic Calorimeter, based on sampling ADC readout and FPGA data filtering. The achieved results will be presented.
        Speaker: Mr Peter Lemmens (KVI, University of Groningen)
        Poster
      • 4:00 PM
        Universal single board tester for investigation of the avalanche photo detectors. 2h 30m
        New electronic single board tester described here allows us to test and compare basic characteristics of new types of the APD (SiPMD, MCAPD, GAPD). The tester was realized in a portable form with graphics LCD and three controls buttons. It can measure statical and dynamical characteristics of the APD. We applied virtual periphery concept for very fast and simple way to measure the S/N resolution and own noise of the APD under investigation. The tester can be useful for long time monitoring.
        Speaker: Dr Vasilii Kushpil (Academy of Sciences of the Czech Republic (ASCR))
        Paper
      • 4:00 PM
        Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade 2h 30m
        The upgrade of ATLAS Liquid Argon (LAr) calorimeter readout calls for an optical link system of 100 Gbps per front-end board (FEB). A high speed, low power, radiation tolerant serializer is the critical component in this system. We are addressing the problem by iterative design previously reported at TWEPP with a commercial 0.25 μm silicon-on-sapphire CMOS technology we have evaluated to be radiation tolerant. In this paper, we present the updates for the design and post layout simulation of a two lane serializer array with each lane runs at 8 Gbps, and a total of 16 Gbps aggregated data rate. A newer process in the same SOS technology has been announced by the foundry for which new simulation results will be presented.
        Speaker: Tiankuan Liu (Southern Methodist University (US))
        Paper
        Poster
      • 4:00 PM
        Use of FPGA embedded processors for high performance data compression 2h 30m
        We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level 0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on-board on DDR2 latency memories and readout upon reception of a Level 0 accept signal. The maximum raw data throughput at the output of the trigger front end cards is 2.6 Gbps. To readout these data over two Gigabit ethernet interfaces we implemented two data compression systems: one based on a simple hard wired zero suppression algorithm implemented in the FPGA and one based on an FPGA embedded processor running a flexible data compression C code. The two algorithms are tested on simulated Monte-Carlo events and compared with respect to maximum achievable readout bandwidth, maximum compression ratio and impact on readout latency.
        Speaker: Dr Roberto Ammendola (INFN Roma Tor Vergata)
        Paper
        Poster
      • 4:00 PM
        VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter 2h 30m
        Charm-meson resonances and yet undiscovered glueballs might reveal the origin of the hadronic mass spectrum. The PANDA collaboration at the future FAIR synchrotron facility at Darmstadt, Germany, will employ antiproton annihilations to investigate resonances in the charmonium mass region. In order to gain high flexibility for physics event selection, a trigger-less data-acquisition system is employed. A sampling ADC (SADC) readout of the PANDA Electromagnetic Calorimeter (EMC) will allow to realize the desired event-selection approach. The developed feature-extraction algorithm, implemented in VHDL for a commercial 16 bit 100 MHz SADC, and the achieved beam-test results will be discussed during the presentation.
        Speaker: Mr Peter Lemmens (KVI, University of Groningen)
        Poster
    • 6:30 PM 7:30 PM
      Walk to Palais Ferstel 1h
    • 7:30 PM 11:00 PM
      Conference Dinner 3h 30m Palais Ferstel

      Palais Ferstel

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
    • 9:00 AM 9:45 AM
      P8 TOPICAL - Level-1 track triggers for the ATLAS high luminosity upgrade Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Livio Mapelli (CERN)
      • 9:00 AM
        Level-1 track triggers for the ATLAS high luminosity upgrade 45m
        The HL-LHC, the planned high luminosity upgrade for the LHC, will increase the collision rate in the ATLAS detector approximately a factor of 5 beyond the luminosity for which the detectors were designed, while also increasing the number of pile-up collisions in each event by a similar factor. This means that the level-1 trigger must achieve a higher rejection factor in a more difficult environment. This talk will discuss the challenges that arise in this environment and strategies being considered by ATLAS to include information from the tracking systems in the level-1 decision. The main challenges involve reducing the data volume exported from the tracking system for which two options are under consideration: a region of interest based system and a intelligent sensor method which filters on hits likely to come from higher transverse momentum tracks.
        Speaker: Elliot Lipeles (University of Pennsylvania)
        Paper
        Slides
    • 9:45 AM 10:30 AM
      P9 TOPICAL - Upgrade of the CMS tracker with Tracking Trigger Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Livio Mapelli (CERN)
      • 9:45 AM
        Upgrade of the CMS tracker with Tracking Trigger 45m
        The planned upgrades of the the LHC and its injector chain are expected to allow operation at luminosities around or above 5x10^34 cm-2 s-1 sometimes after 2020, to eventually reach an integrated luminosity of 3000 fb-1 at the end of that decade. In order to fully exploit such operating conditions and the delivered luminosity, CMS needs to upgrade its tracking detectors and substantially improve its trigger capabilities. To achieve such goals, R&D activities are ongoing to explore options and develop solutions that would allow to include tracking information at Level-1. Some of the options considered are reviewed, discussing their potential advantages and disadvantages.
        Speaker: Dr Duccio Abbaneo (CERN)
        Paper
        Slides
    • 10:30 AM 11:00 AM
      Coffee Break 30m
    • 11:00 AM 11:15 AM
      P10 - xTCA WG Summary Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Stephen Quinton (Rutherford Appleton Laboratory)
      • 11:00 AM
        xTCA 15m
        Speaker: Markus Joos (CERN)
        Slides
    • 11:15 AM 11:30 AM
      P11 - Power WG Summary Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Stephen Quinton (Rutherford Appleton Laboratory)
      • 11:15 AM
        Power 15m
        Speaker: Magnus Hansen (CERN)
        Slides
    • 11:30 AM 11:45 AM
      P12 - Opto WG Summary Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Stephen Quinton (Rutherford Appleton Laboratory)
      • 11:30 AM
        Opto 15m
        Speaker: Francois Vasey (CERN)
        Slides
    • 11:45 AM 12:00 PM
      P13 - MUG and SEU WG Summary Room EI 7

      Room EI 7

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Stephen Quinton (Rutherford Appleton Laboratory)
    • 12:00 PM 12:35 PM
      Close out
      Conveners: Dr Markus Friedl (Institut fuer Hochenergiephysik (HEPHY)-Oesterreichische Akadem) , Philippe Farthouat (CERN)
      • 12:00 PM
        Close Out 35m
        Speaker: Philippe Farthouat (CERN)
        Slides
    • 12:35 PM 2:00 PM
      Lunch 1h 25m
    • 2:00 PM 3:50 PM
      TUTORIAL - Advanced Packaging (Part 1) Kontktraum

      Kontktraum

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Jorgen Christiansen (CERN)
    • 3:50 PM 4:10 PM
      Coffee Break 20m
    • 4:10 PM 6:00 PM
      TUTORIAL - Advanced Packaging (Part 2) Kontaktraum

      Kontaktraum

      Vienna, Austria

      <font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
      Convener: Jorgen Christiansen (CERN)
      • 4:10 PM
        Advanced Packaging (Part 2) 1h
        • Requirements to and technologies for IC packaging. • Overview of different packaging technologies and their specific applications. • Packaging for high reliability applications. • Pitfalls and challenges in IC Packaging. • Advanced 3D packaging (chip on chip / die on die / etc.).
        Speaker: Mr VAL