Sep 26 – 30, 2011
Vienna, Austria
Europe/Zurich timezone

A demonstration of a Time Multiplexed Trigger for CMS

Sep 28, 2011, 11:50 AM
25m
Room EI 7 (Vienna, Austria)

Room EI 7

Vienna, Austria

<font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
Oral Trigger A3b - Trigger

Speaker

Dr Gregory Michiel Iles (Imperial College Sci., Tech. & Med.)

Description

A novel approach to first-level hardware triggering has been studied and a prototype system built. Calorimeter trigger primitive data (~5 Tb/s) are reorganised and time-multiplexed so that a single processing node (FPGA) may access the data corresponding to the entire detector for a given bunch crossing. This provides maximal flexibility in the construction of new trigger algorithms, which will be an important factor in ensuring adequate trigger performance at the very high levels of background expected at the upgraded LHC. A vertical slice of the first level trigger chain is presented, including: the time-multiplexing system, algorithm processors, DAQ functionality and subsequent demultiplexing. The challenges of building what is essentially a 5 Tb/s image processor are explored, along with the potential performance and operational benefits.

Summary 500 words

A new approach to first-level triggering is demonstrated, using a prototype system based on time multiplexing of detector trigger data. This enables, in the case of the CMS detector, the trigger primitive data from the entire calorimeter for a specific bunch crossing (40 MHz) to be processed in a single processing node (FPGA). The data rate exceeds 5Tb/s. This architecture avoids the data-sharing connections between processing nodes that occur in a conventional system in which each node operates on only a portion of the detector with limited overlap between nodes. Furthermore, the trigger algorithms within each processing node have access to the full resolution of the trigger primitives data, providing maximum algorithm flexibility. The described system has been designed for the CMS calorimeter, but because the system does not apply any data reduction until the main processing stage, it is completely generic and can be used for other applications. The system is essentially a very flexible 5Tb/s real-time image processor operating with a latency of ~1 μs, and as such has received interest from other fields (defence).

The system hardware is based on MicroTCA. Communication to the AMC cards is via MicroHAL, a Hardware Access Library (HAL) that provides robust access to the hardware via standard IP-over-ethernet networks. Similarly to the hardware, the software follows a modular design approach. It exhibits efficient use of the network through automatic concatenation, packetisation and queuing of multiple commands and data streams; reliable access over unreliable network protocols via built in error detection and retry capability; and a simple API for integration with hardware control applications. The software makes use of robust telecommunication technology (Erlang) to provide a scalable system that has been extensively tested at realistic scale. The client is implemented directly in firmware without use of a soft or hard CPU, thus simplifying FPGA design and making the design very portable and easy to implement; it includes a simple SoC bus and controller which may be interfaced to a large variety of custom or open firmware cores.

The system resides in a standard, redundant, telecom MicroTCA crate. The primary slot contains a standard commercial MCH for Ethernet, IPMI. The redundancy is not used, but the connectivity of the redundant slot is exploited with an AMC13 card that provides an interface to the experiment. AMC13 slots 1&2 provide services such as clock distribution, fast control/feedback and DAQ. AMC13 slots 3&4 are left free for the user. A common requirement is additional connectivity between AMC slots that can be accomplished with a protocol agnostic cross-point switch.

A full implementation of the CMS first-level calorimeter trigger system will require the bandwidth capability of the newer Xilinx Virtex 7 series FPGAs to remain within the stringent latency constraints of CMS; however, the described prototype system, built around Xilinx Virtex 5 series FPGAs, demonstrates the core firmware and software functionality of a full vertical slice (i.e. time-multiplexing, algorithms, DAQ and demultiplexing). The benefits of such a system are discussed along with the challenges of building it.

This paper covers the Time Multiplexed Trigger part of the CMS Calorimeter Trigger Upgrade program. The Compact Calorimeter Trigger part is covered in a separate paper [1].

[1] P. Klabbers et al. CMS Calorimeter Trigger Phase 1 Upgrade. These Proceedings.

Primary author

Dr Gregory Michiel Iles (Imperial College Sci., Tech. & Med.)

Presentation materials