Sep 26 – 30, 2011
Vienna, Austria
Europe/Zurich timezone

Design and Development of Electronics for the EuXFEL Clock and Control System

Sep 29, 2011, 4:00 PM
2h 30m
Vienna, Austria

Vienna, Austria

<font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
Poster Systems Posters


Dr Erdem Motuk (University College London)


The development of the Clock and Control (CC) hardware and firmware for the EuXFEL DAQ system is presented. The system exploits the data handling advances provided by the new telecommunication architecture standard for physics. The CC is responsible for synchronising the DAQ system to overall system timing. The hardware consists of a DESY designed MTCA.4 board and a UCL designed Rear Transition Module (RTM). Each RTM controls up to 16 Front End Modules (FEMs) for a 1 Megapixel 2D detector. The CC system is designed to provide extendibility and scalability to support future upgrades to the DAQ or larger detectors.

Summary 500 words

The European X-ray Free Electron laser (EuXFEL) facility will generate 27000 coherent and intense X-ray flashes per second with a ~4.5 MHz bunch delivery rate. Each flash is intense enough to produce a full diffractive picture of scattering targets. The detectors for the 2D camera systems will be able to capture up to 5000 images/second with a resolution of 1 MegaPixel. The three detector designs that are being developed (AGIPD, LPD and DSSC) differ in terms of the functionality and the technologies involved in the design, however the overall structure which consists of sensor modules with an ASIC and Front End Modules (FEMs) is similar. The common Clock and Control (CC) system provides the synchronising clock and bunch and train related information to the FEM electronics. It also receives status feedback from and distributes the veto signals to the FEMs to reject some of the detector data.

The CC system consists of a MTCA.4 Advanced Mezzanine Card (AMC) board and a Rear Transition Module (RTM). The MTCA.4 AMC board (DAMC2) is designed by DESY as a multi-purpose FPGA hardware platform for various projects in DESY and provides the processing capability for the CC functionality. We have developed a custom RTM board according to the MTCA.4 standard which connects to the DAMC2 through two thirty-pair Advanced Differential Fabric (ADF) connectors.

The connections to the FEM boards are realised on AC-coupled LVDS links on CAT5 RJ45 cables. The RTM board provides the number of channels to support up to 16 FEM modules for a 1 MPixel 2D detector. Each channel comprises 4 LVDS pairs on an RJ45 connector. The names and the description of these signals are listed below.
• Output clock (FAST clock): A ~99 MHz clock derived from the 4.5 MHz bunch clock.
• Output data (FAST data): Provides the trigger start signal and train ID data to the FEMs.
• Veto: The bunch reject data encoded on a either 99 or 4.5 MHz clock.
• Status: A status feedback from the FEMs

The development and testing of the receiver circuitry required for AC-coupling on the data signal on the FEMs and the status signal on the CCs will also be described.

The CC system receives clock and system information from the EuXFEL Timing Receiver through MTCA.4 crate backplane.

The CC system is designed to provide scalability to support multi-Megapixel detectors by using extra AMC and uRTM board pairs in the same crate with one pair designated as master, and sharing the clock and the data through the MTCA.4 backplane. Each CC board pair takes up two slots (double full-size board) on the crate which comes in either 6 or 12 slot configuration.

The CC hardware and firmware is designed to provide the flexibility, extendibility and scalability to support possible future upgrades to the DAQ or larger detectors. This approach reduces the cost and effort for developing the system by using a general-purpose MTCA.4 FPGA board as its processing platform and an RTM to provide the custom functionality.

Primary authors

Dr Erdem Motuk (University College London) Mr Martin Postranecky (University College London) Mr Matt Warren (University College London) Prof. Matthew Wing (University College London)

Presentation materials