Sep 26 – 30, 2011
Vienna, Austria
Europe/Zurich timezone

3D integration of pixel detectors at VTT

Sep 28, 2011, 2:00 PM
Room EI 7 (Vienna, Austria)

Room EI 7

Vienna, Austria

<font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria


Sami Vaehaenen


Vertical (3D) integration using Through Silicon Vias (TSV) is gaining lot of attention within electronics industry. 3D integrated structures should enhance electrical performance of electronic devices, boost up device miniaturization, and enable new designs and stacks of device layers made with heterogeneous technologies. For pixel detectors, 3D integration using TSVs in combination with edgeless sensors is believed to solve the problem regarding the building large panels with minimal gaps between the individual tiles. VTT is doing R&D in the field of edgeless sensors and advanced interconnects. This presentation gives updates on the separate activities at VTT which are needed for fabrication of 3D integrated pixel detectors using Cu TSVs.

Presentation materials