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Chair: Maria Kastriotou (STFC-ISIS)12/06/2024, 14:00
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Philipp Bender (Infineon)12/06/2024, 14:05
Abstract:
It is long established that terrestrial cosmic radiation (TCR) can lead to the destruction of semiconductor power devices - such as diodes, MOSFETs or IGBTs – for a large range of voltage classes (~ 300 – 7000 V) [1]. The general mechanism are neutron-nucleus collisions that create highly energetic spallation fragments within the device, and which can deposit sufficient energy to...
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Francesco Pintacuda (STMicroelectronics)12/06/2024, 14:25
Abstract:
This study was performed inside the UK-Space Weather Innovation Measurement Modelling Risk (SWIMMR) dedicated to space weather and its effect on terrestrial electronic devices. It was performed in cooperation with ISIS-CHPIR and the Physics and Chemistry Department of Palermo University and STMicroelectronics.
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The cosmic ray impacts in the atmosphere make new particles clusters... -
Shi-Jie Wen (Cisco)12/06/2024, 14:45
Abstract:
For high performance network products and system, the resilience by design to tolerant SEE is vital in terrestrial level application due to large volume of installation in the field. Cisco’s resilience design is based on the rate vs. recovery time that is proportional to the customer impact. We take the beam test as the design validation approach. The network product (hardware +...
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Paolo Rech (Università di Trento)12/06/2024, 15:05
Abstract:
Complex AI accelerators, such as Graphics Processing Units (GPUs) or dedicated accelerators implemented in Field Programmable Gate Arrays (FPGAs) or in Application Specific Integrated Circuits (ASICs), such as the Google’s Tensor Processing Unit (TPU) are rapidly making their way in the chip market. Embedding AI is extremely interesting for automotive, productions lines, and...
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Puneet Gupta (NVIDIA)12/06/2024, 15:25
Abstract:
Soft Error Rate (SER) testing is crucial for evaluating the robustness of advanced process nodes offered by various foundries, particularly those caused by high-energy neutron particles. We derive the Failure In Time (FIT) numbers using a test setup specifically designed to comply with the JEDEC Spec JESD89-3B. This setup is tailored to assess the SER sensitivity of SRAM bit cells...
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12/06/2024, 15:40
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