Speaker
Description
FPGA design is complex, there are many design tools which allow implementing our design. What is missing however, is the step before implementation, architecture. There is no standard industry tool for developing this, instead engineers use a variety of tools from Draw IO to Visio and power point. All unsuited to the task, what is needed is the ability to create the architecture and from that generate the RTL architecture automatically.
Adiuvo has been developing a tool internally called FPGA architect, this tool enables engineers to go from SysML diagram to RTL infrastructure. Creating technology independent solutions which trace back to requirements for safety critical designs. The model is the master, it has full support for AXI and is ale to automatically implement AXI Interconnects from the Adiuvo library. The tool also generate all register maps and interface documentation
This talk will explain how Adiuvo has implemented it and lessons learned from developing 3 FPGA to date.
| Talk's Q&A | During the talk |
|---|---|
| Talk duration | 25'+12' |
| Will you be able to present in person? | Yes |
