Speaker
Description
Positron emission tomography (PET) systems greatly benefit from precise timing measurements, especially in time-of-flight (TOF) applications, which enhance image quality by providing more accurate localization of positron annihilation events. Current commercial TOF systems typically require Time-to-Digital Converters (TDCs) with timing resolutions in the range of 10-20 picoseconds (ps) to achieve an overall coincidence timing resolution of around 200 ps in full width at half maximum (FWHM) between two PET detectors. These precise measurements are accomplished using TDCs. However, as the number of channels increases, particularly in total-body PET systems, the resource demands on FPGAs for TDC implementation grow significantly, leading to higher costs and reduced scalability.
Traditional FPGA-based TDCs rely on Tapped Delay Lines (TDLs) to achieve high-resolution timing. While effective, this approach necessitates the use of multiple TDLs to improve resolution, which significantly increases FPGA resource consumption and limits the number of channels that can be synthesized.
In this work, we propose an ultra-low resource TDC design that utilizes a Look-Up Table (LUT)-based counter as the time measurement unit instead of the conventional TDL approach. Our design achieves a sub-10 ps time resolution, which is comparable to existing TDL-based TDCs, but with a remarkable reduction in resource usage by around 60%. This significant reduction in FPGA resource consumption enables the implementation of more channels on a single FPGA, thereby maintaining system performance while also lowering costs.
Our proposed solution offers a viable path forward for scaling PET systems, particularly for total-body PET applications where the number of channels is a critical factor. By reducing FPGA resource usage while maintaining sub-10 ps timing performance, this method represents a valuable advancement in the development of cost-effective, high-performance PET TOF systems.
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