Speaker
Description
We present advancements in image sensor technology combining Skipper Charge Coupled Devices (Skipper-CCDs) with CMOS imaging techniques to achieve exceptional low-noise and high-speed readout capabilities. The Skipper-in-CMOS image sensor merges the non-destructive readout advantage of Skipper-CCDs with the high conversion gain of a pinned photodiode and integrated in-pixel signal processing within a CMOS process. A 15 × 15 μm² pixel cell in a 200 × 200 array was fabricated using Tower Semiconductor’s commercial 180 nm CMOS Image Sensor process. Measurements demonstrate significant readout noise reduction reaching sub-electron noise levels of 0.15e⁻ for pixel test structures with off-chip readout and deep-sub electron level of 0.075e- with the on-chip integrated read-out chain, thus validating single photon counting capability when exposed to illumination.
Complementing this, the Skipper CCD-in-CMOS Parallel Read-Out Circuit V2 (SPROCKET2) is designed in a 65 nm CMOS process to facilitate high frame rate readout, integrating with pixelated Skipper CCD-in-CMOS sensors. Each SPROCKET2 readout pixel, covering a 60 × 60 μm² area, interfaces with an array of 16 active image sensor pixels. Utilizing correlated double sampling and analog-domain accumulation of ten successive samples, SPROCKET2 achieves low noise, high-speed digitization at 66.7 ksps, with measured Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) of approximately 0.44 LSB and 0.58 LSB, respectively.
Currently, a large-area array consisting of 20,000 SPROCKET2 ADC pixels, designed to multiplex at a 1:16 ratio to 320,000 sensor pixels is being fabricated. By employing a 10.24 Gbps optical data link, the design supports a frame rate of 4 kfps over extensive sensing areas, minimizing deadtime. In simulation, the pixel demonstrates an input-referred resolution of 10 μV in its highest gain mode and consumes 50 μW with a constant current draw to reduce power-rail crosstalk.
Additionally, we showcase the development of pixel detector ASIC readout integration using silicon photonics at both room temperature and cryogenic temperatures (~100 K), addressing future detector challenges through tight integration of sensing, computing, and communication functions. This development involves co-design and optimization of pixel electronics with integrated silicon photonic micro-ring modulators (MRMs), facilitating high-speed optical modulation (10.24 Gb/s per channel) directly at the pixel level.
| Workshop topics | Front-end electronics and readout |
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