2nd FPGA Developers' Forum (FDF) meeting

Enhancing FPGA Verification by Combining VUnit and UVVM

22 May 2025, 14:10

30m

500/1-001 - Main Auditorium (CERN)

HDL verification and simulation tools Verification

Speaker

Mr Markus Leiter (P2L2 GmbH)

Description

This talk explores the synergy between VUnit and UVVM, two leading open-source
verification frameworks for VHDL. UVVM provides a structured approach with powerful
testbench utilities and verification components, while VUnit enhances automation,
advanced test management, and continuous integration support. Additionally, VUnit
enables seamless use of multiple simulators within a single project setup.

The session includes practical examples and best practices to demonstrate how combining
these tools streamlines FPGA verification, improves productivity, and ensures maintainable
and expandable testbenches.