20–23 May 2025
CERN
Europe/Zurich timezone
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Architecting FPGA for low power Leadership

22 May 2025, 14:10
30m
500/1-001 - Main Auditorium (CERN)

500/1-001 - Main Auditorium

CERN

400
Show room on map

Speaker

Dr Hardik Shah (Lattice Semiconductor)

Description

Reducing power consumption in FPGAs offers a range of benefits across various applications, including: extended battery life, simplified heat sink requirements, reduced complexity of the PCB power network, the potential for smaller package sizes, minimized heat-related measurement errors, and increased component longevity. Achieving energy-efficient FPGA design demands a comprehensive approach—from product strategy to the choice of process technology and on-chip architecture. In this talk, the speaker will provide an inside look at how Lattice FPGAs are engineered to deliver significant power savings.

Presentation materials