2nd FPGA Developers' Forum (FDF) meeting

Session

Sharable HDL cores

20 May 2025, 15:40

500/1-001 - Main Auditorium (CERN)

Conveners

Sharable HDL cores

• Filiberto Bonini (CERN)

8. Open Logic – open-source FPGA Standard Library

Oliver Bründler (OpenLogic)

20/05/2025, 15:55

Sharable HDL cores

Open Logic is the fastest-growing open-source HDL standard library on the market, as measured by GitHub stars. It simplifies FPGA development with reusable, modular, and vendor-independent components. Bridging the gap between hand-optimized HDL code and high-level abstractions like HLS and IP integration, it offers a balanced approach to effort and resource optimization. With a strong focus on...

66. Unleashing >100G Performance: High-Speed UDP/TCP Hardware Stacks for FPGAs by CAST

Calliope-Louisa Sotiropoulou (CAST)

20/05/2025, 16:30

As modern digital systems demand increasingly higher data rates, the role of high-throughput, low-latency communication becomes critical in applications such as data acquisition, real-time processing, and high-performance computing. This talk describes how UDPIP and TCPIP hardware protocol stack IP cores can be designed to deliver deterministic, line-rate Ethernet communication in FPGA-based...

48. The PandABlocks framework for flexible run-time configuration of Zynq SoCs

Glenn Christian (Diamond Light Source)

20/05/2025, 17:00

Sharable HDL cores

The PandABlocks framework comprises FPGA gateware, linux kernel and root filesystem for the PS, a TCP server and web-UI. It was originally developed to support the Zynq-7000 based PandABox hardware platform used in beam line scanning applications at several synchrotron light sources for orchestration of motion systems and detectors. The PandA collaboration, consisting of Diamond Light Source,...

24. NDK: An open-source framework for high-speed network applications on FPGAs

Daniel Kondys (CESNET), Radek Iša (CESNET)

20/05/2025, 17:25

Sharable HDL cores

CESNET (Czech Education and Scientific Network) has a long history of providing backbone connectivity and services to institutions such as universities and research centers. One of its subdivisions, tasked with monitoring network traffic, was already familiar with the FPGA technology when 100 GE networks emerged. Soon after, we developed our first FPGA-based network card and firmware to...

41. Error-Redundant Implementation of Commercial IP Cores: A Practical Example

Mr Philipp Jacobsohn (SmartDV)

20/05/2025, 17:55

Sharable HDL cores

The reuse of predefined IP cores is a well-established practice in semiconductor design, offering cost and technical advantages. However, commercial providers must meet diverse implementation requirements, ensuring compliance with specifications while optimizing power, frequency, gate utilization, and feature scope. Additionally, IP cores must function reliably across FPGA and ASIC platforms,...