AXI4 (Memory-Mapped, Stream) is a well established set of flexible bus interfaces. They can support various address and/or data widths, have optional support for bursts, byte strobing, back-pressure, sideband signals, etc.
Writing generic yet easily maintainable AXI-compatible modules is hard: implementation must take care of abiding interoperability rules for optional signals at all times....
In this session we will explain the new disruptive architecture from our new low power, high speed FPGA Families. This architecture is different to the standard FPGA architecture and has a lot of benefits compare to the old architecture.
We will go thru the different FPGA Families which are based on this Quantum architecture and we will work out the benefits for the user if they are using...
ABT has several mixed gateware/software projects, such as its fast interlocks (FIDS) and kicker timing routing (KiTR) systems, that require a specific top-level design for each equipment (e.g. PS KFA45 injection pulse generators) while at the same time also sharing a set of common HDL cores and AXI bus architecture. Git submodules answer the need of common cores well, however also the...
The Electron Ion Collider (EIC) Timing Data Link requires high precision clock recovery for accelerator master clock distribution. To meet the performance requirements a novel method for extracting a low jitter data frame clock from serial encoded data using Xilinx Ultrascale+ transceivers is presented. The frame clock frequency is at the word rate of the serial data link and its phase is...
With the increasing adoption of SoC-based systems at CERN, new initiatives have been put in place to ensure that systems of similar form share as many components (hardware, gateware and software) as possible. As part of the DI/OT framework - now being integrated also into CERN's ATS SoC Common Framework Project - a new standardized build system has been developed to generate boot images for...
I will talk about reset usages in FPGAs and some solutions to practical problems in asynchronous, synchronous and no reset scenarios on different FPGA families. I will point out that the optimum reset usage depends on not only coding styles but also built-in reset features and behavioral differences (e.g. RAM-based vs FLASH-based FPGAs) of the FPGA family in use. Moreover, I will explain how...
The CI4FPGA service aims to provide CERN-based FPGA developers with suitable infrastructure and
pre-configured Docker images for all essential EDA tools, while maintaining high ease of adoption
for its users. This should eliminate the need for individual development teams to deploy and,
importantly, maintain their own solutions. Furthermore, by simplifying access to CI workflows, it
can...
The rise of number of System-on-Chip (SoC) applications in the Accelerators and Technology sector (ATS) motivated the creation of a taskforce in 2023, with the mandate of identifying a generic architecture, common services, and a proper integration in the accelerator control system to converge towards a common SoC framework, starting from the current SoC applications in ATS and future needs....
