Speaker
Description
The Sao Paulo University and the CEA Saclay IRFU teams are developing a new readout ASIC for MPGD detectors, named SALSA. This ASIC is meant to be versatile and adapted to different kinds of MPGD applications like tracking, time projection chambers or photon detection. The 64-channel chip, designed in the TSMC 65nm technology, will integrate preamplifier and shaper front-ends with 12-bit per channel ADC able to reach 50 MS/s sampling rate. The front-end part will be able to manage large capacitance readout electrodes up to 1 nF, with four configurable amplitude ranges from 0-50 fC to 0-5 pC, and 8 peaking times up to 500 ns. An integrated data processing block will take in charge baseline corrections, zero-suppression and feature extraction before to format the data in packets to be transmitted by up to four gigabit links.
The SALSA project was launched in the framework of the EIC project for the readout of ePIC experiment MPGDs. Different prototypes were produced since 2022 to evaluate front-end and ADC blocks, as well as the phase-locked loop (PLL) block that generates internal clocks. A larger prototype, SALSA1, was then produced in 2024 to validate and measure the performance of the front-end - ADC chain, as well as of service blocks. The SALSA2 prototype, which will include the data processing functionalities of the final ASIC but with 32 channels only, is presently under development. It will be submitted in the second half of 2026, and tested from the beginning of 2027. The final pre-series prototype is expected in 2028, for a series production in 2029. After a presentation of the project and the target specifications of the ASIC, major results on the performance of the SALSA1 prototypes will be shown. Then the ongoing development of SALSA2 will be presented, as well as the major steps of the project.
| Name of the speaker | Damien Neyret |
|---|---|
| Eligible for the Georges Charpak Young Scientist Award. | no |