Speaker
Description
In anticipation of higher luminosities at the Belle II experiment, high levels of beam background
from outside of the interaction region are expected. To prevent track trigger rates
from surpassing the limitations of the data acquisition system, an upgrade of the first-level
neural track trigger becomes indispensable. This upgrade contains a novel track finding
algorithm based on three-dimensional Hough transformations of the center wires in the
set of so-called track segments that are crossed by the particle tracks. These track segments
combine eleven close-by wires in hourglass shapes for both the axial and stereo wire
planes of the Central Drift Chamber of Belle II. Using this preselection algorithm, the
track segment information is preprocessed and passed to a deep neural network predicting
the vertex and the azimuthal and polar angles of a three-dimensional particle track.
With this setup, a minimum-bias single track trigger is expected to be considerably more
background resistant than the current implementation with two-dimensional track finding
and single hidden layer networks.
For the upgrade of the neural track trigger, a more powerful 4th generation Belle II
universal trigger FPGA board (“UT4”), compared to the presently used one (“UT3”), is
available. This avoids the time-consuming data transfer between the track finding and the
neural computation. Since both the track finding and neural network parts can now be
executed on the same FPGA board, the gained latency allows for the implementation of
deep neural networks, even with the possibility to include the complete wire input from the
track segments. Implementing in addition a classification output node, both the efficiency
and the background rejection of the neural track trigger can be increased significantly.
The upgraded neural track trigger will be commissioned at the end of 2025 and is planned
to run from the year 2026 onward.
Significance
Our work presents an upgrade of the presently running neural network track trigger of Belle
II, which implements a novel track finding algorithm, followed by a deep neural network
for precise track information. Simulations based on real data show a strongly improved
performance of the upgrade. An implementation on FPGA boards of the algorithms has
been made possible while adhering to the hardware and latency constraints.
| Experiment context, if any | Belle II Experiment |
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