Speaker
Description
After an intensive R&D programme, LHCb approved building of the Downstream Tracker (DWT): a system based on the ''artificial retina'' to pre-reconstruct tracks in the SciFi (the detector downstream to the magnet) at readout level during Run 4. Running before any trigger level, it has to process events at the average LHC crossing rate of 30 MHz.
The ''artificial retina'' is an extremely parallel tracking architecture that ensures low-latency and high-throughput when implemented on FPGAs. Pattern recognition is performed by a set of elemental processing units (cells) specialised in reconstructing tracks near predefined reference tracks. In the DWT implementation, each cell with a track candidate returns as output a fixed-length set of hits that potentially belong to the track.
However, in high-density applications, the output of this ultrafast parallel stage may not be sufficient for an effective pattern recognition; or a more precise parameter evaluation may be necessary as input to further processing. The addition of a fitting stage is therefore necessary, but matching the speed of the fully parallel cell-based pattern-finding stage is a challenge: the fitter stage has to cope with a track candidate rate $\mathcal{O}(30$ GHz$)$, while keeping the latency lower than 1 $\mu$s. In this talk we will discuss how we implemented on FPGA a fully pipelined $\chi^2$ fitter for the DWT that picks the right hits combination from each set, or entirely rejects the track candidate.
This approach allows to keep under control the combinatorial nature of the pattern recognition and achieve an $\mathcal{O}(n)$ time complexity, a feature extremely appealing for LHCb ''Upgrade-II'' (Run 5) that will collect data at the luminosity of $\mathcal{L} = 1.5\times10^{34}\,\mathrm{cm}^{-2}~\mathrm{s}^{-1}$, a factor 7.5 times larger than the Run 4 one.