Speaker
Description
Central Drift Chamber (CDC) in the Belle II experiment is one of the charged tracking device for both offline and real-time hardware trigger systems. Belle II CDC has been using a Front-End Electronics (FEE) device based on Xilinx Virtex-5 FPGA to record the digitized waveform of anode wires and to deliver the data to both central data acquisition system and hardware trigger system. In the operation so far, we observe an issue of background wire hits in the FEE, where bunches of wire hits not caused by charged particles happen in nearby regions. The track finding is based on Hough transformation. Compared to the wire-based offline track finding, the implementation in FPGA for hardware trigger purpose is based on track segment, where hits of multiple wire layers are combined. Due to reduced dimension in track finding, larger mesh size in the conformal plane, and no association to wire drift time and signal waveform, the track trigger is more sensitive to the cross-talk noise, causing a fake trigger rate with a factor of 2 or more. We perform a study of implementing small-scale machine learning in the FPGA of FEE to separate the wire hit signal from background based on the difference of their waveforms. Since the Xilinx Virtex-5 FPGA has less resource than modern series, the challenges are not only the separation power but also reduction on the FPGA resource usage in order to realize the implementation on each of the wire channel within a relatively small FPGA. We will report about the development of the model, FPGA firmware, real deployment and the validation with Belle II system.