Speaker
Description
Dephy is a research and development project supported by the IN2P3 institute, aiming to investigate the technologies required for the development of small-pixel detectors for trackers in future particle accelerators. Among its objectives, the project focuses on designing pixel readout circuits with high timing resolution, capable of operating in extreme radiation environments. For timing-critical applications, the 28 nm CMOS process is of particular interest, as it enables the development of fast pixel designs while offering proven radiation tolerance. The design of the first pixel array prototype will be presented, and its test results will be shown and discussed.
Summary (500 words)
One of the main long-term objectives of the Dephy R&D project is the development of a hybrid pixel array, in which the readout circuit pixels are bump-bonded to an array of fast detectors, such as LGAD-type sensors. The target pixel size is 50 µm × 25 µm. The hit arrival time will be measured with a resolution better than 50 ps RMS, while maintaining power consumption below 1 W/cm². High-resolution TDC circuits will be integrated into the matrix to measure both Time-of-Arrival (ToA) and Time-over-Threshold (ToT) for each hit.
A prototype consisting of a 2 mm × 1 mm mini@asic was submitted in early 2023. It includes test structures designed to characterize the 28 nm CMOS process in terms of radiation tolerance, as well as a small-scale pixel readout circuit.
The pixel readout consists of a matrix of 36 × 12 pixels, each measuring 25 × 12 μm². Each pixel integrates a fast charge-sensitive preamplifier with an NMOS transistor feedback, enabling a constant current discharge. This input stage is followed by a discriminator equipped with a 6-bit DAC to adjust the threshold finely. The bias current of the input stage is programmable in the 2 μA to 20 μA range.
To investigate the impact of sensor capacitance on noise, additional capacitance has been deliberately introduced to the input of selected pixels within the array. The front-end circuitry occupies an area of 20 μm × 12 μm. A charge injection circuit has been implemented to evaluate the performance of the circuit independently of the detector. The system allows for charge injection into a single pixel, a group of pixels, or all pixels simultaneously. A large bandwidth buffer is implemented in the periphery of the chip to measure directly the output of the charge amplifier for a few readout pixels.
All pixels in the matrix, as well as the configuration system, have been confirmed to be functional. S-curves were plotted for the 432 pixels of each chip with a CSA bias current of 8 µA. These curves show a threshold dispersion of 130 e⁻ before tuning, which is reduced to 50 e⁻ after tuning.
In this case, the input-referred noise (ENC) is 25 e⁻ rms with no input capacitance connected, and increases to 45 e⁻ rms with an input capacitance of 100 fF. These values are in good agreement with simulation results.
However, measured jitter is higher than predicted by the simulation. Indeed, for an input charge of 4ke- and an input capacitance of 100 fF, the output hit shows a phase jitter of 150 ps, about 50% higher than the value obtained by simulation. Further work is underway to understand whether the extra jitter is intrinsic to the design or related to the test setup.