Speaker
Description
The High Granularity Timing Detector (HGTD) is a Phase II upgrade project for ATLAS, aimed at providing precise time measurements for tracks to reduce the impact of pile-up effects.
The read-out is performed by ALTIROCA which is a 2x2 cm² CMOS 130nm ASIC with 225 channels.
In order to build the detector, about 27000 ASIC will be produced and tested at the wafer level using a probestation. The poster will describe the acquisition system as well as the results obtained for the pre-production.
Summary (500 words)
The increase in particle flux during the high luminosity phase of the Large Hadron Collider (HL-LHC) and the instantaneous luminosities up to L ≃ 7.5×1034 cm−2 s-1, will significantly impact the performance of the ATLAS detector. Pile-up mitigation is one of the main challenges as 200 interactions per bunch crossing are expected on average. The new High Granularity Timing Detector (HGTD) located in the forward region with pseudo-rapidity range from 2.4 to about 4.0 will provide high-precision timing information that allows to distinguish between collisions occurring close in space but well-separated in time.
The HGTD incorporates two double-sided layers of Low Gain Avalanche Detectors (LGAD) sensors. These sensors are designed to provide timing information for minimum ionizing particles with a time resolution better than 70 ps per hit (equivalent to 50 ps per track at the end of its operational lifetime), crucial for accurately assigning particles to their respective vertices.
This ASIC is bump-bonded onto a 15 x 15 channel matrix 1.3 mm x 1.3 mm LGAD sensor and operates in a highly irradiated environment (200 MRad and 2.5 x 1015 neq/cm2 fluence). Each channel of the ASIC integrates a 1 GHz bandwidth preamplifier, followed by a high-gain leading-edge discriminator and two TDC used for Time-of-Arrival and Time-Over-Threshold measurements, along with a 35 µs depth memory. Zero suppression is implemented at pixel level. The ASIC also provides luminosity measurements. Timing data are output at a rate up to 1.28 Gb/s and luminosity data at 640 Mb/s to the DAQ. The ASIC has been designed full Digital-On-Top and is triplicated to ensure its robustness against SEE.
Five prototype versions of the ASIC have been designed, produced and tested. ALTIROCA is the final version satisfying all specifications criteria, including radiation tolerance. In order to build the detector, about 27000 ASIC will be produced and tested at the wafer level using a probestation. Since a 12 inch wafer contains 124 ASIC, about 220 wafers need to be tested. The tests will be performed at two sites sharing the production equally. The aim of these tests is to check that the ASICs are functional and meet the performance requirements (jitter, noise, luminosity,...) before the hybridization.
A dedicated acquisition system has been designed including a commercial FPGA board, a custom interface board and a custom probe card. This system is duplicated at the two sites, the only difference being the model of the probe station.
The poster will describe the acquisition system, the testing procedure as well as the results obtained for the pre-production corresponding to 5% of the production at the two sites.ko
