Speaker
Description
High-speed serial transmitters are commonly used in various fields, including high energy physics experiments, where the data volume has significantly increased due to detector upgrades. We present a CMOS-logic serializer core designed for front-end detector data transmission in a 55 nm technology. The prototype design features a 32-to-1 binary-tree multiplexer, an LC-based phase-locked loop, and a current-mode logic driver. The total jitter at 10.24 and 11.09 Gbps is approximately 24.5 ps and 30 ps, respectively, with power consumption of 96.2 mW and 97.4 mW. The internal timing margin accommodates a power supply variation from 1.15 V to 1.4 V.
Summary (500 words)
High-speed serial data transmission is essential in high-energy physics experiments, serving as a universal data link and enabling data readout for pixelated readout electronics and high-density integrated circuits, such as time-to-digital (TDC) and analog-to-digital (ADC) modules. For instance, the proposed Circular Electron Positron Collider operates at a system clock frequency of 43.33 MHz, requiring a single-channel data rate of 11.09 Gbps. Additionally, a high-data-width serializer core can support the integration and operation of more channels at high event or sampling rates in TDC or ADC circuits.
A serializer prototype core is built on a CMOS-logic binary-tree structure, incorporating a low-jitter LC-tank phase-locked loop (LC-PLL) and a fully CMOS-logic multiplexer (MUX32t1) with a multi-stage current-mode logic (CML) driver, based on a 55 nm technology. Figure 1 illustrates the architecture. The LC-PLL, based on a previously validated design, operates within a frequency range of 4.74–5.92 GHz and achieves a random jitter of less than 0.46 ps at 5.12 GHz. To support data rates exceeding 10 Gbps, the MUX32t1 employs a cascaded binary-tree architecture with five meticulously optimized stages. The first four stages utilize ordinary 2:1 logic cells, while the final stage, operating over 5 GHz, incorporates a high-speed 2:1 cell to meet stringent timing requirements. With data rates above 10 Gbps, the unit interval is less than 100 ps, leaving minimal timing margin for serialization. This necessitates precise setup and hold times (approximately 20 ps), making it challenging to satisfy timing constraints across all process, voltage, and temperature (PVT) corners, especially in worst-case scenarios. To mitigate this, a simple delay selection circuit is integrated into the 5 GHz clock paths for corner adjustments.
The serializer demonstrated stable operation at 5.12, 10.24, and 11.09 Gbps, with total jitter values of 16.1, 24.6, and 30 ps, respectively. The measured random and total jitter of the PLL were approximately 0.33 and 8 ps at 5.12 GHz, and 0.42 and 13.7 ps at 5.55 GHz, slightly higher than those of the initial design. Phase noise was measured at -104 dBc/Hz at a 1-MHz offset from the 5.12 GHz carrier. Total current consumption was 79 mA at 11.09 Gbps, with the majority of power attributed to high-speed clock transmission and serial data driving. The current data driver consists of a CML driving stage and a 5-stage pre-amplifier, drawing a total current of 38 mA with a static output current of 4.8 mA, resulting in low driving efficiency. A second prototype, optimized with a source-series-terminated driver expected to reduce power consumption, is currently under development and will be submitted in July 2025. Additionally, the current PLL will be modified to support a wider frequency range and flexible frequency multiplication and division factors. Further test results and design optimizations will be presented.
