Speaker
Description
ASICs are now indispensable in High-Energy Physics, powering everything from ultra-low-noise front ends to high-speed data aggregation under extreme radiation. But designing them for detectors is nothing like commercial chip development: every project is unique, resources are thin, and mistakes often surface only after tapeout or production.
This talk looks at the pitfalls we’ve encountered—broken analog models, incomplete verification coverage, unexpected power density issues, and specifications that evolve faster than the chips themselves. More importantly, it distills these hard lessons into practical guidelines: adopt Digital-on-Top flows, validate models as rigorously as designs, design for verifiability and testability, and plan for specifications that will change.
The goal is simple: to help future HEP ASIC projects avoid repeating past mistakes, and to move from fragile, one-off developments toward sustainable engineering practices that still leave room for innovation.
Bio – Davide Ceresa
Davide Ceresa is an electronics engineer at CERN specializing in microelectronics and digital ASIC design for high-energy physics applications. He earned his Ph.D. in Electronic Devices through a joint POLITO–CERN program, focusing on intelligent particle tracking systems. Previously, he completed a Master's in Nanotechnologies for ICTs (POLITO–INPG–EPFL) and a Bachelor's in Physics Engineering (POLITO).
Since joining CERN in 2012, Davide has played key roles in designing, testing, and producing custom integrated circuits for particle detectors. As the main designer of the CMS Outer Tracker MPA chip, he led its development from concept to industrial production and testing. He also served as ASIC working group convener for the CMS Outer Tracker Phase-II upgrade.
Currently, Davide serves as deputy leader of the CERN EP R&D work package on IC technologies. In this role, he defines research priorities, leads design and testing teams, and guides technology development for next-generation detectors. His work bridges the gap between research and application, bringing advanced ASIC methodologies—such as Digital-on-Top flows and radiation-tolerant design—to the HEP community.
Beyond his technical work, Davide mentors colleagues, supports projects through the CHIPS program, and champions best practices in ASIC development to strengthen the long-term sustainability of HEP microelectronics.
