High-speed serial transmitters are commonly used in various fields, including high energy physics experiments, where the data volume has significantly increased due to detector upgrades. We present a CMOS-logic serializer core designed for front-end detector data transmission in a 55 nm technology. The prototype design features a 32-to-1 binary-tree multiplexer, an LC-based phase-locked loop,...
This paper presents performance of readout electronics for the ATLAS muon-chamber (MDT) to detect and measure the charge resulting from proton-proton collisions. The design emphasizes speed, robustness, and efficiency in area and power. It achieves a peaking time of 15 ns with 60-pF detector capacitance and 4 ns without it. The circuit demonstrates linear sensitivity of 1 mV/fC at the...
This report presents a single-channel readout chip LATRIC0 designed for the CEPC Out Tracker detector. The chip integrates an event-driven ring oscillator time-to-digital converter in a 55 nm process, achieving an average bin-size of 28.9 ps for both time over threshold and time of arrival. The average power consumption for measurement is below 1 mW. To mitigate the inconsistencies between...
During LHC Long Shutdown #3, the base layer quench detectors for the LHC main dipoles will be upgraded to a new type. The new FPGA-based quench detectors are equipped with two galvanically isolated, high-resolution input stages that digitise the two dipole aperture coil voltages. This new digital design allows the quench detection settings to be changed remotely. As the detectors are installed...
In this work we report on the development of a Shunt LDO (SLDO) for use in the serial powering chain of staves at the Electron Ion Collider (EIC). The device is designed in a 110nm CMOS technology and can supply up to 1A at a voltage of 1.1 to 1.4V. Simulated PSRR at DC is -56dB. Safety features such as load overcurrent protection and the ability to shunt the current of failed parallel SLDOs...
This paper examines the latest advancements in power supply technologies for the HL-LHC, particularly focusing on the EASY6000 power supply system. Highlighted for its enhanced radiation tolerance, the system supports safe and efficient operations over the HL-LHC's extended lifespan. The study evaluates the system's performance in challenging environments, essential for optimizing power...
This work evaluates how stage count, gate length, and load capacitance tuning affect radiation tolerance in CMOS inverter based ring oscillators using a newly developed Dynamic Voltage-Dependent (DVD) Single-Event Transient (SET) model validated in a 65\,nm CMOS technology. The model captures n- and p-type Single Event Phase Transients (SEPTs). Simulations are performed under worst-case...
The CALOROC1B ASIC has been designed to read out the SiPMs for the ePIC detector at the EIC collider. Each of its 36 channels is composed of a high-gain preamplifier, two low-power preamplifiers, a dynamic gain switching mechanism, a shaper, and two ADCs to read the energy, with a discriminator connected to a TDC for time-of-arrival measurements. This work presents the ASIC architecture and...
The High Luminosity LHC upgrade demands enhanced tracking, prompting a full replacement of ATLAS’s Inner Detector with the all-silicon Inner Tracker (ITk). Spanning 33–291 mm from the beam pipe, ITk will use hybrid pixel detectors with 65 nm CMOS chips. The inner region, facing extreme radiation, will feature 3D pixel sensors, while the outer regions use planar sensors. Testing in 2024–2025...
This work presents the design, implementation, and characterization of a 28 nm CMOS readout channel for pixel sensors in future HEP experiments. The channel adopts the Time-Over-Threshold technique for the digital conversion of the detector signal amplitude and integrates a low-noise, charge-sensitive amplifier based on a composite cascode gain stage. A prototype chip, featuring an 8x32 array...
The bPOL48V is a DC-DC Point-Of-Load (POL) buck converter developed at CERN and characterized at RWTH Aachen University under the DRD7 program. The bPOL48V is designed to address power distribution challenges of next-generation high-energy physics experiments by enabling power delivery at higher voltages and lower currents in supply cables, thereby minimizing power losses. It supports a higher...
In this work, MALTA2 sensors were tested at the CERN SPS Test Beam using the MALTA beam telescope, as well as with a pulsed laser employing the Edge Transient Current Technique (Edge-TCT). Sensors irradiated up to a fluence of $5 \times 10^{15}~1~\mathrm{MeV}~n_{\mathrm{eq}}/\mathrm{cm}^2$ were characterized in terms of tracking efficiency and cluster size, using the grazing angle technique....
Motivated by the Upstream Pixel tracker in the LHCb Upgrade II and future electron-positron collider, COFFEE series chips are developed in a 55nm HVCMOS process. While maintaining a fine spatial resolution and reasonable power consumption, we aim to achieve a few nanosecond timing under hit density up to 100 MHz/cm$^2$. Building on the first validation chip with in-pixel amplification, a new...
This work presents the design of a radiation-tolerant driver for high-speed electro-optical transmitters. The driver delivers 25 Gb/s modulation signals with a 3.6 V swing, bridging the voltage gap between 28 nm CMOS technology (rated for 0.9 V) and silicon-photonics devices. A multi-voltage domain approach allows operation from a single supply, optimizing power efficiency and minimizing area....
High-energy physics experiments require radiation-tolerant optical links for high-speed data communication. Ring modulators offer high bandwidth but are sensitive to temperature and process variations, necessitating thermal control to stabilize their resonant wavelengths. This work presents a radiation-tolerant thermal control unit designed for micro-ring modulators. The system integrates a...
The upgrade of the ALICE vertex detector (ITS3) with wafer-scale stitched MAPS targets an orthogonal MIP detection efficiency >99%, with a fake-hit rate <0.1pixel⁻¹s⁻¹ and a power budget of 40mW/cm². The MOSS wafer-scale monolithic sensor analog front-end, featuring ~0.55mV/e- gain and ~16e- rms of noise and threshold dispersion, was designed, prototyped and measured confirming these...
The new version of ToASt as a radiation tolerant readout for silicon microstrips sensors, has been produced and it is now under characterization. It is implemented in a 110 nm commercial CMOS technology, and it is synchronous to a 160 MHz clock. A common time stamp is used to provide both particle time of arrival and energy particle information with ToT technique. Triple logic is applied to...
The development of lightweight flex PCBs and nanowire-based thermal interfaces for low-mass, high-performance detector modules are presented. A novel manufacturing approach enables flex circuits with double-sided pad access, assembled using ACF and gold studs. Signal integrity was simulated and validation trials conducted on test structures. For thermal management, sintered and glued nanowire...
Abstract (100 words)
The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL. The ETROC2 chips have been extensively tested, and the results have been presented at last TWEPP. We will present here new results including the bump bonding yield improvement study, the time walk correction (WTC) generality study with...
This work presents the Total Ionising Dose (TID) radiation assessment of HV-CMOS pixel sensors fabricated in the LFoundry 150 nm process. Two prototypes, UKRI-MPW1 and RD50-MPW4, were irradiated with X-rays up to 100 Mrad while biased and operated under designed conditions. Post-irradiation measurements on UKRI-MPW1 revealed increased leakage current, reduced breakdown voltage, and parasitic...
This work presents radiation-tolerant implementations for the SALSA front-end readout ASIC through redundancy methods applied to two median-finding algorithms designed for coherent noise suppression. Bit-wise Median Finder (BWMF) and Combinatorial Sum Median Finder (CSMF) were implemented in TSMC 65nm and IHP 130nm technologies and evaluated in terms of area, power, latency, and flip-flop...
We present the initial findings of a silicon photomultiplier powered by a laser and exposed to a light source. The study will explore various parameters of both the laser and the photomultiplier.
This paper presents the design of high-speed readout controller dedicated for pixel detectors. Communication with imaging sensors is asymmetric in its nature. Configuration, calibration and control data transfers are typically not time-critical or are composed of relatively short commands. In the other direction, it is desired to transfer image data as fast as possible. Having that in mind,...
This work presents a 12-bit ADC implemented in 65 nm CMOS technology, designed for on-chip conversion in high-energy physics experiments, It is also intended for use as an IP block within the DRD7 collaboration framework. The architecture features a fully differential Capacitive DAC, a double-tail latched comparator and an asynchronous digital controller. Post-layout simulations demonstrate an...
Results are presented for the measurement of Single Event Upset (SEU) rate and recovery demonstration for the Kintex-7 FPGA on Thin Gap Chamber (TGC) readout boards for the ATLAS experiment at HL-LHC. The readout boards were installed on the TGC detectors in the ATLAS detector area. We observed 133 single-bit and 5 multi-bit SEU errors in the configuration memory of the Kintex-7 FPGA during...
MightyPix is a novel high-voltage monolithic active pixel sensor developed for the proposed LHCb Mighty-Tracker. It is designed to handle hit rates up to 40 MHz/cm² with 3 ns timing precision and a high radiation tolerance with NIEL and TID of up to 3×10^14 neq/cm² and 40 MRad. Building on prior prototypes MightyPix1 and LF-MightyPix, MightyPix2 integrates a segmented matrix architecture with...
Data-driven readout architectures produce unsorted streams of data packets with variable latency. Reconstructing an event frame, defined as grouping packets from the same time window, requires a sorting operation. Its complexity increases proportionally to the occupancy and distance between the packets’ source and the sorting step.
This contribution presents an on-chip bucket sorting module...
The waveform sampler in the CMS ETROC2 chip for LGAD gain aging monitoring is a 2.56-GS/s 12-bit 8x-Interleaved ADC that consists of a coarse SAR stage, and a fine stage. This architecture delivers high performance on a relatively modest 65 nm process, while requires finding up to 24 calibration constants through calibration. We developed an automatic calibration method using charge...
The performance of the new CAEN controller R6060 was measured on a real slice of the ATLAS RPC detector, using 15 Easy3000 modules of various types, and compared with the present controller A1676A. An average improvement of a factor 30 was found for the response time of the single command execution, and of about 5 for the parameter refresh. Considering the test setup, an additional factor of...
The PRISME chip is developed as a new radiation tolerant PLL for clock generation with a jitter lower than ten ps. This block is designed in the TSMC 65 nm technology, to allow its integration in future readout ASICs that are considered for the EIC project. The PLL block is a basis of a low-power standalone clock fan-out ASIC with phase adjustment capabilities. A first prototype was design and...
The High Granularity Timing Detector (HGTD) is a Phase II upgrade project for ATLAS, aimed at providing precise time measurements for tracks to reduce the impact of pile-up effects.
The read-out is performed by ALTIROCA which is a 2x2 cm² CMOS 130nm ASIC with 225 channels.
In order to build the detector, about 27000 ASIC will be produced and tested at the wafer level using a probestation....
The HL-LHC upgrade will lead to increased radiation levels in the LHC tunnel. Consequently, hundreds of vacuum gauge conditioning electronics deployed throughout the LHC must be replaced by new radiation tolerant designs. The development of radiation tolerant electronics followed the CERN radiation hardness assurance protocol. Component and system-level radiation tests have been performed at...
At CERN, for the High-Luminosity upgrade of the Large Hadron Collider (LHC), the cryogenics instrumentation team will produce 2,000 electronic cards to support 1,800 new instrumentation channels. These cards will integrate with the LHC’s existing infrastructure of 10,000 transducer cards and are therefore designed to be radiation tolerant. This paper describes the results of two irradiation...
The INFN IGNITE project plans to implement a large-area ASIC (order 1-2 cm2) aimed at fast 4D-tracking. System pixels are required to have pitch below 50 µm and time resolution better than 30 ps. In the present paper we present measurement results concerning the performance of the two prototype ASICs, the Ignite32 and the Ignite64, designed to readout respectively 32x32 and 64x64 pixel...
SALSA1 is a test chip preparing the SALSA design, a reconfigurable readout ASIC for MPGD detectors designed in TSMC 65 nm. SALSA1 includes different analogue, mixed and digital blocks to be tested to evaluate the best options for SALSA. The chip is highly reconfigurable to adapt to a large diversity of situations, managing different gains, polarities and different peaking times, expected to...
The SALSA chip will be a versatile ASIC designed for various MPGD applications, including TPCs, trackers, and photon counting. It will feature 64 channels with tunable front-ends and fast ADCs, and a configurable DSP for data correction and feature extraction. The frontend includes a high open loop gain CSA, a pole-zero cancellation circuit, and a shaper, with four dynamic ranges and eight...
The ALICE ITS3 upgrade at CERN replaces the innermost vertex detector layers with six self-supporting, half-cylinder MAPS sensors.
This concept introduces new electrical and mechanical challenges addressed by a custom flexible printed circuit (FPC). The FPC distributes eight 10.24 Gb/s signals, control lines, and five power supplies for 24 segments, enables a semi-cylindrical transition,...
We studied the Total Ionizing Dose (TID) response of LSF0102 2-channel voltage translators intended for the upgrade of the ATLAS Muon Barrel read-out system for HL-LHC. TID tests were carried out at the CERN CC60 facility using a 60Co gamma source. The devices showed no degradation in key performance metrics, including supply current, eye diagram quality, rise/fall time, jitter, and bit error...
We present the development of an Ultra-Fast Silicon Pixel Detector (UFSPD) for Phase II of the Mu3e experiment, which aims to detect the rare decay of a muon into three electrons. To achieve the required sensitivity of $10^{−16}$, enhanced time and vertex resolution are essential. The UFSPD should replace the Phase I SciFi detector and targets a time resolution of ~100 ps. The first test...
Open-source design tools can play a very important role in the High-Energy Physics community. These tools offer a cost-effective alternative to proprietary EDA software, promoting reproducibility, collaboration, and long-term accessibility. This work presents a mixed comparison of three blocks — a Common-Mode Noise Filter (CMNN), Finite State Machine (FSM), and a VCO — designed using an...
The ALICE ITS3 project develops a wafer-scale monolithic stitched pixel detector chip of 27~cm lengths. One of the main challenges in such a design is to transmit data from the 144 pixel matrices (or tiles) to the Left End-Cap (LEC) region where the readout processor is located, without compromising power consumption, noise coupled into front-ends, and the active pixel area. This contribution...
Description
We present the design and first test results for SPIDER_v0, the first ASIC prototype in CMOS TSMC 65nm designed for the time measurement path of LHCb Electromagnetic Calorimeter after LS4 Upgrade. The main requirements are a time resolution of 15ps, and an occupancy up to 30% (12 Mevent/s).
SPIDER_v0 is a 2-channel waveform digitizer allowing time reconstruction by digital...
