WIT2012 Workshop on Intelligent Trackers

Session

Real time pattern-recognition and advanced algorithms

5 May 2012, 08:00

INFN Pisa

27. A clusterization algorithm for ATLAS pixel upgrade.

Teddy Todorov (Centre National de la Recherche Scientifique (FR))

05/05/2012, 08:30

On-module electronic circuits (3D and conventional), intra-module and off-detector communication

The increase in the LHC luminosity and the reduction of the pixel size foreseen for the ATLAS pixel upgrade leads to an increased amount of data generated by the pixel detector at each beam crossing. The bandwidth of the readout should be upgraded to deal with this increase of data, to keep a good detector efficiency. Another approach, studied at LAPP, consists in decreasing the amount of...

46. A Self Seeded First Level Track Trigger for ATLAS

Andre Schoening (Ruprecht-Karls-Universitaet Heidelberg (DE)), Sebastian Schmitt (Ruprecht-Karls-Universitaet Heidelberg (DE))

05/05/2012, 09:00

Real time pattern-recognition and advanced algorithms

For the planned high luminosity upgrade of the Large Hadron Collider, aiming to increase the instantaneous luminosity to 5-7 x 10^34/cm^2/s, the implementation of a first level track trigger has been proposed, which could be installed in the year 2020/21 along with the complete renewal of the ATLAS Inner Detector. The fast readout of the hit information from the Inner Detector is...

42. Use of Associative Memories for L1 triggering in LHC environment.

Daniel Magalotti (INFN Sezione Perugia (IT))

05/05/2012, 09:30

Real time pattern-recognition and advanced algorithms

Modern high energy physics experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly exclusive selections to efficiently select the rare events inside the huge background. In the framework of the CMS experiment at LHC one of the identified challenges for future...

31. The new variable resolution Associative Memory for Fast Track finding

Alberto Annovi (Istituto Nazionale Fisica Nucleare (IT))

05/05/2012, 10:00

Real time pattern-recognition and advanced algorithms

We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. We have developed this device using 65 nm technology combining a full custom CAM cell with standard-cell control logic. The customized design maximizes the pattern density, minimizes the power consumption and...

6. 3D Vertical Integration Technology for Fast Pattern Recognition

Tiehui Ted Liu (Fermilab)

05/05/2012, 11:00

Real time pattern-recognition and advanced algorithms

Hardware-based pattern recognition for fast triggering on particle tracks has been successfully used in high-energy physics experiments for some time. The CDF Silicon Vertex Trigger (SVT) at the Fermilab Tevatron is an excellent example. The method used there, developed in the 1990’s at Pisa, is based on algorithms that use a massively parallel associative memory architecture to identify...

57. Pattern recognition with vector-type detector hits

Dr Rudolf Frühwirth (ÖAW, HEPHY Vienna)

05/05/2012, 11:30

Novel types of "intelligent" trackers provide hits consisting of position-cum-direction rather than position alone. We study several types of track finding algorithms in this context, for example the Hough transform, neural networks, a cellular automaton, track following, and the combinatorial Kalman filter. The performance of the algorithms is compared on simulated data in a simplified...

64. Discussion

05/05/2012, 12:00