Mark Pesaresi
(Imperial College Sci., Tech. & Med. (GB))
04/05/2012, 11:30
The CBC is a 130 nm CMOS chip designed for the readout of short silicon microstrips for the CMS Phase II tracker upgrade. It is a 128 channel wire-bonded chip which can be DC coupled to sensors of either polarity. The replacement tracker is also expected to provide limited tracking information to the Level 1 hardware trigger. With a binary front end the chip is well suited to adapting for use...
Dr
Marvin Johnson
(Fermilab),
Marvin Johnson
(Fermi National Accelerator Lab. (US))
04/05/2012, 12:00
On-module electronic circuits (3D and conventional), intra-module and off-detector communication
We preset a design of a front end ASIC that combines a level 1
trigger and normal event readout. It uses asynchronous logic through
out the design to reduce both power consumption and noise sensitivity.
The only clock used is the 40 MHz LHC clock. A test chip based on
this design is planned to be submitted in July of this year.
Andreas Wassatsch
(MPI Physik / HLL)
04/05/2012, 12:30
Real time pattern-recognition and advanced algorithms
The grouping of data elements based on characteristic relations is known as clustering.
It can either be used for data compression in a DAQ chain, or even to calculate the characteristic trigger input values based on event data.
Driven by the requirements of the PXD detector in the Belle II experiment @KEK/Japan, a real-time clustering engine was developed.
This software-inspired hardware...
Davide Braga
(STFC - Science & Technology Facilities Council (GB))
04/05/2012, 14:30
On-module electronic circuits (3D and conventional), intra-module and off-detector communication
We present the design of a new version of the CBC (CMS Binary Chip) ASIC for the readout of CMS Tracker Phase-two upgrade. CBC2, designed in 130nm CMOS, doubles the input channels to 254 and will be bump-bonded to the substrate. The ASIC is designed to instrument double layer modules in the outer tracker, consisting of two overlaid silicon sensors with aligned microstrips, and incorporates the...
Mr
Mitch Newcomer
(University of Pennsylvania)
04/05/2012, 15:00
On-module electronic circuits (3D and conventional), intra-module and off-detector communication
A viable seeded track trigger for a high rate collider detector environment must have excellent angular precision, response times commensurate with beam crossing rate and low mass. We have designed a fast clustering block servicing 128 contiguous strips to be included in an LHC upgrade silicion strip readout ASIC with these objectives in mind. The block is based on the presence of an...
Vladimir Gromov
(NIKHEF)
04/05/2012, 15:30
Real time pattern-recognition and advanced algorithms
The TimePix3 chip, currently being designed, is a pixel read-out chip with precision tdc (< 2 ns) recording hit arrival times and time-over-threshold. The read-out architecture [1] allows for
continuous and trigger-free readout of sparsely distributed data with the rate up to 20 Mhits cm^-2 s^-1. It is designed for both solid-state pixel sensors and gaseous detectors. When used with gaseous...
Mr
Hans Kristian Soltveit
(Ruprecht-Karls-Universitaet Heidelberg (DE))
04/05/2012, 16:30
On-module electronic circuits (3D and conventional), intra-module and off-detector communication
The data transfer rate from highly granular tracking detectors are limited today by the available bandwidth in the readout links what prevents the detectors to be used for fast triggering.
MMwave technology is the next generation wireless technology that can provide multi-Gbps wireless connectivity for short distances between electronics [1]. Since the carrier frequency is higher (60 GHz),...
Prof.
KK Gan
(Ohio State University)
04/05/2012, 17:00
On-module electronic circuits (3D and conventional), intra-module and off-detector communication
Parallel optical engine allows a compact design for high-speed data transmission. The design is enabled by the readily available high-speed VCSEL arrays. With the use of a 12-channel array operating at 10 Gb/s per channel, a parallel optical engine can deliver an aggregated bandwidth of 120 Gb/s. With the spacing of 250 mm between two VCSELs, the width of a VCSEL array is only 3 mm. This...
