Conveners
B2: Programmable Logic, design tools and methods
- Magnus Hansen (CERN)
Dr
Jinyuan Wu
(Fermilab)
18/09/2012, 14:50
Oral
A digitization scheme of sub-microampere current using a commercial comparator with adjustable hysteresis and FPGA-based Wave Union TDC has been tested. The comparator plus a few passive components forms a current controlled oscillator and the input current is sent into the hysteresis control pin. The input current is converted into the transition times of the oscillations, which are...
Maximilian Buchele
(Albert-Ludwigs-Universitaet Freiburg (DE))
18/09/2012, 15:15
Oral
The GANDALF 6U-VME64x/VXS module has been developed to cope with a variety of readout tasks in nuclear physics experiments and is amongst others operated at the COMPASS experiment at CERN. Based on this platform, we present a 128-channel TDC which is implemented in a Xilinx Virtex-5 FPGA using the shifted-clock-sampling method. Compared to well-known FPGA designs based on delay-lines, usually...
Steffen Staerz
(TU Dresden)
18/09/2012, 15:40
Oral
In the context of upgraded read-out systems for the Liquid-Argon Calorimeters of the ATLAS detector, modified front-end, back-end and trigger electronics are foreseen for operation at the High-Luminosity LHC. Accuracy and efficiency of the energy measurement and reliability of pile-up suppression are substantial when processing the detector raw-data in real-time. Several digital filter...
Dr
Michael Traxler
(GSI Helmholtz Centre for Heavy Ion Research)
18/09/2012, 16:05
Oral
One of the most important aspects of particle identification experiments is the digitisation of time, amplitude and charge data from detectors. These conversions are done mostly with Application Specific ICs (ASICs). However, the recent developments in Field Programmable Gate Array (FPGA) technology allow us to use commercial electronic components for the required Front-End Electronics (FEE)...
