Conveners
III.a FE & ASICs: Session 1
- Marek Idzik (AGH University of Science and Technology (PL))
III.a FE & ASICs: Session 2
- Xavi Llopart Cudie (CERN)
III.a FE & ASICs: Session 3
- Xavi Llopart Cudie (CERN)
Prof.
Kock Kiam Gan
(Ohio State University (US))
6/4/14, 11:00 AM
Data-processing: 3a) Front-end Electronics
Oral
Planned upgrades to the LHC at CERN will increase its energy and luminosity. These advancements will require increasing the optical data communication bandwidth to fully exploit the accelerator and detector upgrades. This require much increased per-fiber output data rates of up to 10 Gb/s. While 10 Gb/s optical links are mature in industry, as yet there are none that have sufficient radiation...
Jingbo Ye
(Southern Methodist University, Department of Physics)
6/4/14, 11:20 AM
Data-processing: 3a) Front-end Electronics
Oral
We report an ASIC development based on a commercial 0.25-micron silicon-on-sapphire CMOS technology. This ASIC is a dual channel serializer sharing one LC-PLL with 8 Gb/s each channel and a total data throughput of 16 Gb/s for each chip. The prototype packaged in QFN is measured from 7.2 to 8.5 Gb/s each channel, limited by the tuning range of the PLL. This design is for an optical link that...
Dr
Krzysztof Piotr Swientek
(AGH University of Science and Technology (PL))
6/4/14, 11:40 AM
Data-processing: 3a) Front-end Electronics
Oral
The multichannel 6-bit ADC ASIC with data serialization was designed in view of LHCb Tracker System Upgrade. The first prototype was designed and fabricated in CMOS 130 nm technology. The main chip components are 8 channels of fast, very low power (<0.5 mW per channel) 6-bit SAR ADCs, data serialization circuitry based on ultra-low power internal PLL and fast SLVS I/O differential interface....
Mr
Matthew Andrew
(University of Hawaii)
6/4/14, 12:00 PM
Data-processing: 3a) Front-end Electronics
Oral
Extremely fast timing from Micro-Channel Plate PhotoMultiplier Tubes
(MCP-PMTs) and multi-gigasample per second (GSa/s) waveform sampling
ASICs will allow precision timing to play a pivotal role in the
next-generation of Ring Imaging Cherenkov (RICH) detectors. We have
developed a second prototype of the electronics to instrument the Time
of Propagation (TOP) counter for the Belle II...
Elliot Hughes
(Rutgers, State Univ. of New Jersey (US))
6/4/14, 12:20 PM
Data-processing: 3a) Front-end Electronics
Oral
The CMS experiment at the CERN Large Hadron Collider (LHC) will upgrade the photodetection and readout systems of its hadron calorimeter (HCAL) through the second long shutdown of the LHC in 2018. A central feature of this upgrade is the development of two new versions of the QIE (Charge Integrating Encoder), a Fermilab-designed custom ASIC for measurement of charge from detectors in high-rate...
Mr
Matteo Cardinali
(Johannes Gutenberg-Universitaet Mainz), Dr
Matthias Hoek
(Johannes Gutenberg-Universitaet Mainz)
6/5/14, 4:10 PM
Data-processing: 3a) Front-end Electronics
Oral
High-precision single photon timing with resolutions well below 100 ps is becoming increasingly important. It enables new detector designs, like the Time-of-Propagation DIRC of Belle II, or the TORCH upgrade for LHCb, and to improve existing designs, e.g. allow chromatic corrections in DIRCs. These applications have in common a high channel density, limited available space and low power...
Mrs
Sylvie BLIN
(OMEGA Ecole Polytechnique&CNRS/IN2P3)
6/5/14, 4:30 PM
Data-processing: 3a) Front-end Electronics
Oral
The SPACIROC ASIC is designed for the JEM-EUSO fluorescence-imaging telescope on board of the International Space Station. Its goal is the detection of Extreme Air Showers (EAS) above a few 10^19 eV, developing underneath at a distance of about 400 km, in the troposphere. The SPACIROC family is dedicated to readout 64-channel Multi Anode PMT (MAPMT) or similar detectors. The two main features...
Dr
Christophe De La Taille
(OMEGA CNRS/IN2P3 et Ecole Polytechnique (FR))
6/5/14, 4:50 PM
Data-processing: 3a) Front-end Electronics
Oral
PETIROC2 is a 32 channel readout ASIC for high speed readout of SiPM matrixes. It features a 1 GHz 20 dB preamp followed by 1 GHz high speed discriminator and time-to-amplitude converter to measure the time down to 50 ps. A variable shaper channel measures the charge over 10 bits and also feeds a discriminator for high level signal trigger. The time and charge signals are digitized internally...
Matthew Noy
(CERN)
6/5/14, 5:10 PM
Data-processing: 3a) Front-end Electronics
Oral
The TDCPix is a hybrid pixel detector readout ASIC designed for the
NA62 GigaTracker detector. The requirements are a single-hit timing
resolution better than 200ps RMS, a hit loss of less than 1% in the
presence of a (highly non-uniform) beam rate up to 1MHz/cm^2. This hit
rate leads to an expected data rate at the output of the chip which
can reach 6Gb/s.
The TDCPix comprises an...
Claudio Gotti
(Universita & INFN, Milano-Bicocca (IT))
6/5/14, 5:30 PM
Data-processing: 3a) Front-end Electronics
Oral
The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of about 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultiplier tubes (Ma-PMTs), and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The...
Tetsuichi Kishishita
(University of Bonn)
6/6/14, 11:00 AM
Data-processing: 3a) Front-end Electronics
Oral
The Belle II experiment, which will start after 2015 at the Super-KEKB accelerator in Japan, will focus on the precision measurement of the CP-violation mechanism and on the search for physics beyond the Standard Model. To cope with considerably increased background, a pixel vertex detector (PXD) based on DEPFET technology has been developed.
The PXD consists of two layers of DEPFET sensor...
Dr
Michael Cooney
(University of Hawai'i at Manoa)
6/6/14, 11:20 AM
Data-processing: 3a) Front-end Electronics
Oral
Readout of micro-channel plate detectors using cross strip anodes require low noise, fast charge sensitive amplifier (CSA) front-end electronics. The goal of this CSA project is to improve noise and shaping time from the "PreShape32" amplifier ASIC of the RD-20 collaboration at CERN, presently used in the readout system. A target noise of 100e- + 50e-/pF (<1000e- noise overall) with <100ns...
Mr
Aleksandr Kotelnikov
(Budker Institute of Nuclear Physics)
6/6/14, 11:40 AM
Data-processing: 3a) Front-end Electronics
Oral
The real-time processing of the electron beam parameters is a necessary procedure to optimize the key characteristics of the synchrotron radiation source using feedback loops. The actual problem is to study multi-bunch beam instabilities. To solve this problem a high-speed electron beam profile monitor is developed. This device includes a photodetector unit and signal recorder. The...
Dominik Dannheim
(CERN)
6/6/14, 12:00 PM
Data-processing: 3a) Front-end Electronics
Oral
The CLIC vertex detector must have excellent spatial resolution, full geometrical coverage extending to low polar angles, extremely low mass, low occupancy facilitated by time-tagging, and sufficient heat removal from sensors and readout. These considerations, together with the physics needs and beam structure of CLIC, push the technological requirements to the limits and imply a very...
Massimiliano De Gaspari
(CERN)
6/6/14, 12:20 PM
Data-processing: 3a) Front-end Electronics
Oral
Timepix3 is a unique ASIC developed to provide fast readout in a low to medium hit rate environment. The pixel matrix consists of 256x256 pixels with a pitch of 55μm. The chip can be configured in either data driven or frame-based modes. In data driven mode the chip sends out a 48-bit package every time a pixel is hit while the shutter is open. This packet contains 18bits of Time-Of-Arrival...
