15–19 Sept 2008
Naxos - GREECE
Europe/Athens timezone

Development and Testing of an Advanced CMOS Readout Architecture dedicated to X-rays silicon strip detectors

18 Sept 2008, 16:15
2h
Naxos - GREECE

Naxos - GREECE

Speaker

Prof. Stylianos Siskos (Aristotle Univ. of Thessaloniki, Physics Dept., Electronics Lab.,)

Description

An advanced VLSI analog readout architecture, dedicated for X-ray imaging. Critical design issues such as the noise optimization and the shaper implementation technique are addressed and the first test results of a fabricated prototype in a 0.35 μm 3.3 V CMOS process are presented. Important feature of the design is the novel CR-RC2 pulse shaper configuration since in this section, transconductor circuits are used in order to provide a broad range of continuous variable peaking time, programmable gain and adjustable undershoot while still maintaining the noise performance and the required linearity of the specific radiation detection application.

Summary

Using the leapfrog filter design methodology and the Semi Gaussian shaping theory an advanced front end analog processor for a particular X-rays radiation detector was proposed. The specific processing channel consists of a low noise pre-amplification block and a pulse shaping stage and has been designed for multi-channel radiation detectors with capacitance ranging from 1 to 10 pF. In the specific ASIC a novel shaping filter topology based on operational transconductance amplifiers is addressed. Some design considerations and the noise optimization of the pre-amplification stage are also presented. The total IC readout system compatibility to the stringent nuclear spectroscopy requirements is examined performing measurements that confirm its satisfactory performance. The architecture although it provides a relatively long peaking time, is fully integrated and appears to be greatly flexible since the use of OTAs as the topology building cells results to externally adjustable characteristics. Considering the architecture measured performance, the prototype provides peaking time 1.81 μs, conversion gain of 3.3 mV/fC and enc (e- rms) of 382 e- + 21 e-/pF. The system consumes 1mW and the occupied area of the full VLSI structure is 0.2017mm2. Characterization of the analog processor and measurement results are presented supporting the theoretical analysis and confirming that the system operates according to design specifications and can be used for nuclear spectroscopy applications.
Concerning future improvements, the shaping filter can be even more optimized mainly in terms of the linearity and the power dissipation performance. Better linearity results can be obtained at the cost of power dissipation by increasing the power supply rails. Additionally, it can also be improved in terms of the OTA circuit since several low power and low voltage advanced design techniques are available in the IC literature.

Author

Dr Thomas Noulis (Aristotle Univ. of Thessaloniki, Physics Dept., Electronics Lab.,)

Co-authors

Dr Gerard Sarrabayrouse (Laboratoire d’Analyse et d’Architecture des Systèmes LAAS – CNRS, 7 Avenue du colonel Roche, 31077 Toulouse cedex 4, France) Prof. Stylianos Siskos (Aristotle Univ. of Thessaloniki, Physics Dept., Electronics Lab.,)

Presentation materials