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Description
Summary
This paper presents the Data Acquisition (DAQ) System for the Step-1 phase of the E14 experiment, a high energy physics kaon experiment at the Japan Particle Accelerator Research Complex (J-PARC). The goal of the experiment is to measure the rate of the rare decay KL->pi0 nu nubar. This flavor changing neutral current decay is predicted by the Standard Model to happen only once every 3.3x10*11 KL decays. If not observed or observed at a rate very different from the predictions, it will shed light on the mechanism responsible for CP in the quark sector.
The front-end electronics comprises over seventeen 6U VME Crates, and includes three distinctive blocks:
- The Cesium Iodide (CsI), using custom 14-Bit, 125MHz ADC Modules, with 16 channels per module. This block has up to 3,000 Channels.
- The Veto Detectors, using the same custom 14-Bit, 125MHz ADC Modules, fitted with a different firmware. This block has up to 512 channels.
- The Beam Hole Phase Veto, using custom 12-Bit, 500MHz ADC Modules, with 4 channels per module. This block has up to 100 channels.
In the CsI Calorimeter, every analog pulse generated by the photomultiplier tube (PMT) is amplified and passed through a 10-pole filter/shaper with a cutoff frequency of about 10 MHz, which converts the fast PMT pulse into a Gaussian form, while keeping the total energy information constant. The filter/shaper was calculated for optimal Full Width Half-Height (FWHH) of the resulting shape with respect to fitting and timing. After shaping, each pulse is applied to a sample-and-hold ADC chip.
Digitized data are processed locally with field programmable gate arrays (FPGAs), Altera EP2S60F1020C5 chips from the STRATIX II family that perform the board total energy calculation and determine real-time board energy related values. These values are passed through the crate's backplane to custom Transition Boards for successive summing in the crate. The result is a crate-level energy value, which is sent over to the Trigger Supervisor Module, for final decision, and eventual trigger pulse generation.
Each ADC module is provided with a pipeline, up to 4us (500 samples) long, which stores the acquisitions while awaiting the system trigger pulse. After a trigger, data are packed and buffered for readout. In this experiment, events happen in 0.75 second long "spills", followed by 2.65 second long periods of no activity. All events acquired in the 0.75 second spill can be stored in the on board 32 MBytes SRAMs. This allows readout only during the no activity period, to improve the overall signal-to-noise performance. The readout can be performed via the VME32/64 backplane, or via an optional front panel optical link.
Sampling for all calorimeter channels is simultaneous on one low jitter system clock.
In conclusions, this DAQ System is designed to accommodate the particular requirements for the JParc KL Experiment, such as signal conditioning with 10-pole filters that convert narrow PMT signals into Gaussian shaped pulses with optimal FWHH; low input noise; powerful real-time processing with on board FPGAs, and relatively small overall size.
