Speaker
Description
Summary
The NA62 experiment at the CERN SPS aims at measuring the ultra-rare kaon decay K+ → π+νν as a highly sensitive test of the Standard Model (SM) and a search for New Physics. The detection of this process is very difficult due to the smallness of the signal and the presence of a very large background. NA62 aims to collect about 100 signal events in 2 years of running. The devices used for this purposes are a general-purpose trigger and data acquisition board (TEL62) and its mezzanine cards (TDCB) hosting high-performance TDC chips.
The TDCB houses 4 HPTDC chips developed at CERN, receiving from the front-end electronics the discriminated signals whose leading and trailing times are measured with 100ps LSB. The data are then buffered before being read periodically by the on-board FPGA, which adds a time-stamp and a counter to the data stream and addresses it to the TEL62. Several other features are implemented in the TDCB firmware, including a TDC data simulator for testing purposes, the possibility of triggering front-end board calibration signals through an output line and the controller for two on-board 2 MB SRAM memories.
The TEL62 is the main device of the NA62 TDAQ; about 100 cards will be installed on the experiment. The board architecture is based on a star topology: 4 Pre-Processing (PP) FPGAs are connected to a single SyncLink (SL) FPGA. The 4 PPs are directly connected to the 4 mezzanines, for a total of 512 input channels. The amount of data arriving from the TDCs can be up to a few tens of MB/s per channel, depending on the sub-detector. Data are organized in packets, each one related to time frames of 6.4 us duration. The PP has the duty of collecting and merging the data and then of organizing them on the fly in a 2GB DDR2 memory, where each page is related to a well defined 25 ns window. Whenever a trigger arrives the data within a programmable number of 25 ns time windows around the trigger timestamp are collected and sent to the SL. The PP data are merged and synchronized inside the SL, pre-processed and stored in a 1MB QDR SDRAM which sends data packets through 4 Gigabit Ethernet links hosted on a custom daughter card to a computer farm that performs additional cuts and eventually writes events to permanent storage.
The system has been extensively tested at the end of 2012 during the NA62 Technical Run. The TALK board, a TEL62 multifunction daughter board, has been used as L0 Trigger Processor (L0TP): it merges trigger primitives arriving from several subdetectors and sends trigger decisions back. The TALK board design was started by the need to provide a trigger interface between the TTC and the old NA48 trigger distribution system, in order to read the LKr calorimeter with the NA48 readout hardware during the Technical Run. Additional functions in the firmware have been added: driver for the calibration of the calorimeter, test bench controller for the characterization of the new CREAM boards for the LKr readout, and prototype of L0TP. The board has been designed around a Cyclone 3 FPGA, with 5 Ethernet interfaces driven by the Marvell 88e1111 chip and using the Ethernet MAC IP core from More-than-IP. A 1M-16bit word memory is available. As trigger distribution, the board sends trigger requests received from the TTCrx interface to the LKr readout and in addition a list of timestamps is stored in a memory which is readout at the end of burst and sent to the LKr readout PC farm for the event stamping.. The prototype L0TP implements the logic to receive both NIM triggers and primitive packets generated by TEL62s, received through some of the five Ethernet channels. Communication with the PC is also done through an Ethernet interface. Besides the operation as a daughter board for the TEL62, we have developed a 6U VME frame to use the TALK board inside a VME crate.
