Gian Mario Bilei
(Universita e INFN (IT))
9/23/13, 2:20 PM
Oral
Prof.
Giancarlo Mantovani
(INFN)
9/23/13, 2:40 PM
Oral
Rainer KAESMAIER
(Lfoundry)
9/23/13, 3:45 PM
Oral
Technology development and applications for integrated circuit manufacturing are focusing on twofold areas, the 1st one going the aggressive trend of miniaturization, the 2nd going moderate in smaller feature sizes however with wide range of diversification and customization.
In the 2nd area challenges are in fields like integration of different technology platforms such as “CMOS combined...
Antonio Maffucci
(University of Cassino and Southern Lazio)
9/23/13, 5:00 PM
Oral
Given their physical limits, conventional materials such as copper are expected to fail in meeting many of the requirements for future nanoscale IC interconnects. Due to their outstanding electrical, thermal and mechanical properties, Carbon Nanotubes (CNTs) or Graphene Nano-Ribbons (GNRs) are proposed as innovative interconnect materials.
This presentation will first discuss the first...
Frederick Bordry
(CERN)
9/23/13, 5:45 PM
Oral
The LHC has been delivering data to the physics experiments since the first collisions in 2009. The first long shutdown (LS1), which started on 14 February 2013, was triggered by the need to consolidate the magnet interconnections so as to allow the LHC to operate at the design energy of 14 TeV in the centre-of-mass for proton–proton collisions. It has now become a major shutdown that, in...
Jakub Moron
(AGH University of Science and Technology (PL))
9/24/13, 9:50 AM
Oral
The design and preliminary measurements results of 10-bit Successive Approximation Register (SAR) Analog to Digital (ADC) converter are presented. The prototype of the SAR ADC was designed and fabricated in 130 nm IBM technology. Preliminary measurements show that the ASIC is functional and the obtained ENOB (effective number of bits) is of about 9.2 bits. Power consumption of the ADC is...
Matteo Di Cosmo
(Ministere des affaires etrangeres et europeennes (FR))
9/24/13, 9:51 AM
The MicroTCA and AdvancedTCA industry standards are candidate platforms for modular electronics for the upgrade of the current generation of high energy physics experiments. The PH-ESE group at CERN launched in 2011 the xTCA evaluation project with the aim of performing technical evaluations and eventually providing support for commercially available components. Different devices from...
Manoel Barros Marin
(CERN)
9/24/13, 10:15 AM
The Gigabit Link Interface Board (GLIB) project is an FPGA-based platform for users of high-speed optical links in high energy physics (HEP) experiments. The project delivers hardware, firmware/software and documentation as well as provides user support. These resources facilitate the development of evaluation platforms of optical links in the laboratory as well as triggering and/or data...
Jorgen Christiansen
(CERN)
9/24/13, 10:15 AM
Oral
The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than +/- 0.9 LSB and...
Miroslav Havranek
(Universitaet Bonn (DE))
9/24/13, 11:10 AM
Oral
Upgrade of luminosity of the LHC (HL-LHC) imposes severe constraints on detector tracking systems in terms of radiation hardness and ability to cope with high hit rates. One possible way of keeping track with increasing luminosity is usage of more advanced technologies. Ultra deep sub-micron CMOS technology allows design of complex and high speed electronics with high integration density. In...
Olivier Raymond Bourrion
(Centre National de la Recherche Scientifique (FR))
9/24/13, 11:11 AM
Microwave Kinetic Inductance Detector (MKID) are a promising solution for space-borne mm-wave astronomy. To optimize their design and reduce the impact of the primary Cosmic Rays interaction with the substrate, the phonon propagation in the silicon substrate must be studied. A dedicated fast readout electronics, using channelized Digital Down Conversion for monitoring up to 16 MKIDs over a...
Daniele Felici
(Universita e INFN Roma Tor Vergata (IT))
9/24/13, 11:35 AM
Oral
The availability of a sub 1-W SerDes for future LHC read-out systems is of paramount importance. This work relates to the design of two alternative architectures for the critical serializer block within a SerDes with the objective of achieving a power consumption of less than 30 mW at the operating speed of 4.8 Gbit/sec. Two alternative architectures are implemented using a commercial 65nm...
Dirk Wiedner
(Ruprecht-Karls-Universitaet Heidelberg (DE))
9/24/13, 11:35 AM
The Mu3e experiment searches for charged lepton flavor violation in the rare decay mu->eee with a projected sensitivity of 10^-16. Precise measurement of the decay product momentum, decay vertex and time is necessary for background suppression at rates of 10^9 muons/s. This can be achieved by combining an ultra-lightweight pixel tracker based on HV-MAPS with two timing systems. The...
Matteo Mario Beretta
(Istituto Nazionale Fisica Nucleare (IT))
9/24/13, 12:00 PM
Oral
The AMchip is a VLSI device that implements the associative memory function, a special content addressable memory specifically designed for high energy physics applications and first used in the CDF experiment at Tevatron. The 4th generation of AMchip has been developed for the core pattern recognition stage of the Fast TracKer (FTK) processor: a hardware processor for online reconstruction of...
Steffen Muschter
(Stockholm University)
9/24/13, 12:00 PM
During the shutdown of the ATLAS scintillating Tile calorimeter (TileCal) in 2013/14 one of its ondetector electronic modules will be replaced with a compatible hybrid module, which also serves as a demonstrator for future upgrades. This is being built to fulfill all requirements for the complete upgrade of the TileCal electronics in 2022 but augmented to stay compatible with the present...
Frederic Morel
(IPHC/CNRS/IN2P3)
9/24/13, 2:50 PM
A detector, equipped with 50 um thin CMOS Pixel Sensors (CPS), is being designed for the upgrade of the Inner Tracking System (ITS) of the ALICE experiment at LHC. Two CPS flavours, MISTRAL and ASTRAL, are being developed at IPHC aiming to meet the requirements of the ITS upgrade. The first is derived from the MIMOSA28 sensor designed for the STAR-PXL detector. The second integrates a...
Johannes Philipp Grohs
(Technische Universitaet Dresden (DE))
9/24/13, 2:51 PM
The Phase-I luminosity upgrade of the LHC, planned for 2018, requires an improved trigger performance of the LHC detectors in order to suppress increasing pile-up noise. In the Phase-I upgrade of the read-out electronics of the ATLAS LAr Calorimeters high-granularity signals are provided to the Calorimeter trigger system for improved trigger feature extraction. The general design of the future...
Pierpaolo Valerio
(CERN)
9/24/13, 3:15 PM
Oral
A prototype hybrid pixel detector ASIC whose design is tuned to the requirements of a vertex detector for CLIC is described and first electrical measurements presented. The chip has been designed using a commercial 65 nm CMOS technology and comprises a matrix of 64 x 64 square pixels each measuring 25 um on the side. The main features include simultaneous 4-bit measurement of...
Johan Alme
(Bergen University College (NO))
9/24/13, 3:15 PM
The RCU2 - A Proposed Readout Electronics Consolidation for the ALICE TPC in Run 2
Author:
Johan Alme
Bergen University College
On behalf of the the ALICE TPC Collaboration
This paper presents a proposed optimization of the ALICE TPC readout for running at full energy in the Run 2 period after 2014. During these three years an event readout rate of 400 Hz with a low dead time...
Massimiliano De Gaspari
(CERN)
9/24/13, 3:40 PM
Oral
This front-end contains a single-ended preamplifier with a structure for leakage current compensation, suitable to both signal polarities. Preamplifier and discriminator are required to be fast, to allow a Time-of-Arrival measurement with a resolution of 1.56ns. Time-Over-Threshold (TOT) is also measured; the monotonicity of TOT with respect to the input charge is greatly improved as compared...
Riccardo Travaglini
(Universita e INFN (IT))
9/24/13, 3:40 PM
The upgrade of the ATLAS experiment at LHC foresees the insertion of an innermost silicon layer, called Insertable B-layer (IBL). IBL read-out system will be equipped with new electronics. The Readout-Driver card (ROD) is a VME board devoted to data processing, configuration and control. A pre-production batch has been delivered in order to perform tests with instrumented slices of the overall...
Juan Mauricio Ferre
(University of Barcelona (ES))
9/24/13, 5:00 PM
Poster
This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with a 4ps jitter and 18ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise...
Claudio Gotti
(INFN and Univ. of Milano Bicocca (IT))
9/24/13, 5:01 PM
Poster
The CLARO-SiGe is a prototype ASIC for single photon counting with
pixellated photomultipliers, designed to sustain a high counting rate at low power.
Each channel is made of a charge amplifier to readout the current
pulses on a low impedance node and a discriminator with a settable
threshold to count the pulses above threshold.
The architecture of the whole channel is differential.
The...
Elia Conti
(Universita e INFN (Perugia, IT))
9/24/13, 5:02 PM
Poster
The technical challenges related to increased collision rates of the LHC will significantly affect detector electronics design. Efficient hit processing is achieved in pixel detectors by grouping pixel chips in regions, which share buffering logic. We present an approach to determine an optimized sharing strategy between pixels, depending on the shape of clustered hits in the detector. Simple...
Miroslaw Firlej
(AGH University of Science and Technology (PL))
9/24/13, 5:03 PM
Poster
The design and measurements results of low power Phase-Locked Loop (PLL) prototype for applications in particle physics detectors readout systems are presented. The PLL fabricated in 130nm IBM technology was designed and simulated for frequency range 10MHz-3.5GHz. Internal voltage controlled oscillator (VCO) should work in 16 frequency ranges/modes, switched either manually or automatically....
Tobias Harion
(Kirchhoff-Institut Heidelberg)
9/24/13, 5:05 PM
Poster
STiC is a mixed mode readout ASIC for Silicon-Photomultipliers developed in the UMC 180nm CMOS technology. The chip has been designed for the EndoToFPET-US project and aims at providing a high timing resolution to high energy physics and medical imaging applications. The signal is read out and discriminated by a dual threshold method. A low threshold discriminator provides a high precision...
Yunan Fu
(Univerisity of Bonn)
9/24/13, 5:06 PM
Poster
Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256 x 256 pixels organized in a square pixel-array with 55um pitch. Oscillators running at 640MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter...
yang You
(Southern Methodist University)
9/24/13, 5:07 PM
We present single-event-hardened phase-locked loop for structured-ASIC and digital delay-locked loop for DDR2 memory interface applications. The PLL covers a frequency range from 12.5 MHz to 500 MHz with an RMS jitter of 4.7 pS. The DLL operates at 267 MHz and has a phase resolution of 60 pS. Designed in 0.13 µm CMOS technology, the PLL and the DLL are hardened against SEEs for charge...
Patrick Pangaud
(Centre National de la Recherche Scientifique (FR))
9/24/13, 5:10 PM
Poster
To face new challenges brought by the upgrades of the Large Hadron Collider at CERN and of ATLAS pixels detector, for which high spatial resolution, very good signal to noise ratio and high radiation hardness are needed, 3D Integrated Technologies are investigated. Commercial offers of such technologies are only very few and the 3D designer's choice is as a consequence strongly constrained. We...
Heiko Engel
(Johann-Wolfgang-Goethe Univ. (DE))
9/24/13, 5:21 PM
Poster
The ALICE experiment uses custom FPGA-based computer plug-in cards as interface between the optical readout link and the PC clusters of Data Acquisition (DAQ) and High-Level Trigger (HLT). The previous cards for DAQ and HLT have been developed as independent projects and are now facing similar problems with obsolete major interfaces and limited link speeds. A new common card has been developed...
Wilco Vink
(NIKHEF (NL))
9/24/13, 5:22 PM
Poster
The LHCb experiment studies B-decays at the LHC. The Outer Tracker straw tubes detects charged decay particles. The on-detector electronics will be upgraded to be able to digitize and transmit drift-times at every LHC crossing without the need for a hardware trigger. FPGAs have been preferred to application-specific integrated circuits to implement dead-time free TDCs, able to transmit data...
Nicola De Simone
(INFN Rome)
9/24/13, 5:23 PM
Poster
The NA62 experiment at CERN SPS aims to increase the precision in the measure of the Branching Ratio of the K+->pi+nu nubar decay. The required background suppression level due to the decay K+->pi+pi0 can be achieved, among the others, implementing the photon veto in the angular range [1,10] mrad by using a LKr calorimeter. This paper deals with the implementation of the LKr L0 trigger peak...
Dimitrios Marios Kolotouros
(University of Ioannina (GR))
9/24/13, 5:34 PM
Poster
A new generation FPGA-based Timing-Trigger and Control (TTC) system based on emerging Passive Optical Network (PON) technology is being investigated to potentially replace the existing off-detector TTC system used by the LHC experiments. The new system must deliver trigger and data with low and deterministic latency as well as a recovered bunch clock with picosecond-level jitter. It also...
Alexander Paramonov
(Argonne National Laboratory (US))
9/24/13, 5:35 PM
Poster
We report on the development of a new commercial off-the-shelf optical transceiver as a candidate for the transmission of data from the detector to the counting room for experiments at the Large Hadron Collider (LHC). The device is manufactured by Molex using CMOS integrated silicon photonics developed by Luxtera. A transceiver contains four RX and four TX channels operating at 10 Gbps each,...
Todd Brian Huffman
(University of Oxford (GB))
9/24/13, 5:36 PM
Poster
We present results on all aspects of fibre reliability after exposure to the expected doses at HL-LHC. The results for the cold Radiation Induced Attenuation (RIA) are reviewed. The results of new studies of the effect of radiation on fibre bandwidth and mechanical reliability are presented. The fibre bandwidth was studied using measurements of chromatic dispersion and Differential Mode Delay...
Chonghan Liu
(Southern Methodist University)
9/24/13, 5:37 PM
Poster
We present a small-footprint dual-channel optical transmitter module called MTx for the High-Luminosity LHC experiments. The MTx module consists of two separate commercial transmitter optical sub-assemblies (TOSAs) and a dual-channel laser driver ASIC. We have demonstrated that the module prototypes can operate at 10 Gbps using commercial 10 Gbps laser diode drivers. We are developing an 8...
Sarah Seif El Nasr
(University of Bristol (GB))
9/24/13, 5:38 PM
Poster
We report on the results of a radiation test carried out using 20 MeV neutrons on optoelectronic components, such as multi-channel transmitters and Si photonics building blocks, for use in future-data transmission links by experiments at the High-Luminosity LHC.
Ivo Polak
(Acad. of Sciences of the Czech Rep. (CZ))
9/24/13, 5:39 PM
Poster
We report on electronic design of new calibration and monitoring system developed for the scintillator tiles calorimeter (AHCAL) for the ILC. System is based on original fast (3 ns pulsewidth) and precise LED driver called QMB. LED driver uses unique Quasi-Resonant circuit with embedded toroidal inductor. The QR-LED driver creates sinusoidal pulse to drive the LED. It has high dynamic range of...
Agostino Lanza
(INFN Pavia (IT))
9/24/13, 5:50 PM
Poster
Prototypes of DC/DC converters were designed and built with the aim of satisfying the foreseen working parameters in the Phase 2 LHC experiments, using both MOSFETs and more recent devices like SiC and GaN transistors. Optimization of their design, based on the comparison between the simulated and measured thermal, electrical and mechanical performance, is in progress, and many improvements...
Waclaw Karpinski
(Rheinisch-Westfaelische Tech. Hoch. (DE))
9/24/13, 5:51 PM
Poster
A novel powering scheme based on the DC-DC conversion technique will be exploited to power the CMS Phase-1 pixel detector. DC-DC buck converters for the CMS pixel project have been developed, based on the AMIS5 ASIC by CERN. We will show the performance of these devices, including efficiency and line and load regulation at various temperatures. Reliability studies based on a preseries of 200...
Ahmed Bassalat
(Universite de Paris-Sud 11 (FR))
9/24/13, 5:52 PM
Poster
During the shutdown 2013/14, for the enhancement of the current ATLAS Pixel Detector a fourth layer (Insertable B Layer, IBL) consisting of 14 staves is being built and will be installed between the innermost layer and a new beam pipe. A new read out chip
generation has been developed and two different sensor designs, a rather conventional planar
and a 3D design, have been flip chipped to...
Giovanni Mazza
(INFN sez. di Torino)
9/24/13, 6:00 PM
Poster
The Silicon Pixel Detector (SPD) of the PANDA experiment is the closest one to the interaction point and therefore the sensor and its electronics are the most exposed to radiation. The Total Ionizing Dose (TID) issue has been addressed by the use of a deep-submicron technology (CMOS 0.13 um) for the readout ASICs. While these technology are very effective in reducing radiation induced oxide...
Alessandro Bartoloni
(Universita e INFN, Roma I (IT))
9/24/13, 6:01 PM
Poster
The CMS Electromagnetic Calorimeter (ECAL) has played a vital role in the discovery of the Higgs Boson and other physics requiring the precise detection and measurement of electrons and photons. It is a homogenous lead tungstate scintillating crystal calorimeter with on-detector electronics based mainly on CMOS 0.25um ASICs and rad-hard gigabit optical links. The ECAL provides sums of energy...
Christian Faerber
(Ruprecht-Karls-Universitaet Heidelberg (DE))
9/24/13, 6:02 PM
Poster
This paper describes radiation studies of SRAM-based FPGAs as a central component of the electronics for a possible upgrade of the LHCb Outer Tracker readout electronics to a frequency of 40 MHz. Two Arria GX FPGAs were irradiated with 20 MeV protons to radiation doses of up to 7 Mrad. During and between the irradiation periods the different FPGA currents, the package temperature, the...
Frederic Bruno Magniette
(Ecole Polytechnique (FR))
9/24/13, 6:11 PM
Poster
A DAQ system is developped within the SiW Ecal CALICE collaboration. It provides a flexible and scalable architecture, compound of three parts. A detector interface (DIF) extracting data from frontend electronics and sending them as packets. Two levels of data concentration, control clock and fast command fanout. The two cards, named DCC and GDCC, use respectively FastEthernet and...
Daniel Esperante Pereira
(Universidad de Valencia (ES))
9/24/13, 6:12 PM
Poster
Active pixels sensors based on the DEPFET technology will be used for the innermost vertex detector of the future Belle-II experiment. The increased luminosity of the e+e- SuperKEKB collider entails challenging detector requirements, namely: low material budget, low power consumption, high precision and efficiency, and a huge readout rate. The DEPFET active pixel technology has shown to be the...
Stefano Meroli
(Universita e INFN (IT))
9/24/13, 6:13 PM
Poster
The consolidation and upgrade of the cabling infrastructure of the CERN accelerator complex is one of the most critical activities of the LHC Long Shutdown 1. This implies an extraordinary challenge in terms of project management, resource and activity planning, quality control and manpower organization. About 1000 km of both copper and optical fiber control cables have to be newly installed...
Michele Caselle
(Karlsruhe Institute of Technology)
9/24/13, 6:14 PM
Poster
The recording of coherent synchrotron radiation requires DAQ systems with high temporal resolution. To resolve ultra-short terahertz pulses emitted by single bunch YBCO superconducting thin film detectors have been developed. A novel data acquisition system for sampling of the individual ultra-short terahertz pulses with high accuracy and real-time data processing is presented. The DAQ system...
Pablo Moreno
(Universidad de Valencia)
9/24/13, 6:15 PM
Poster
TileCal is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider at CERN. The main upgrade of the LHC to increase the instantaneous luminosity is scheduled for 2022. The High Luminosity LHC, also called upgrade phase-2, will imply a complete redesign of the read-out electronics in TileCal. In the new read-out architecture, the front-end electronics aims to...
Dedalo Marchetti
(Universita' di Roma Tre)
9/24/13, 6:16 PM
Poster
Cosmology studies call for accurate measurements of cosmic microwave background radiation anisotropies. A promising technique to achieve the required precision is based on big arrays of Kinetic Inductance Detectors (KID). In this paper, we describe, a new strategy to stimulate and read a KID array of 128 pixels based on FPGAs and analog to digital converters. The project can reach an analog...
Alessandro Cardini
(Universita e INFN (IT))
9/24/13, 6:17 PM
Poster
The LHCb collaboration is currently working on the upgrade of the experiment to allow, after 2018, an efficient data collection while running at an instantaneous luminosity of 2x1033/cm2s-1. The upgrade will allow 40 MHz detector readout, and events will be selected by means of a very flexible software-based trigger. The muon system will be upgraded in two phases. In the first phase, the...
Thomas Lenzi
(Universite Libre de Bruxelles (BE))
9/24/13, 6:18 PM
Poster
For the LHC high luminosity phases new triple-GEM detectors should be installed in the CMS muon endcap spectrometer, together with a new readout system. The functional requirements on the system are to provide both triggering and tracking information. In addition the system will be designed to take full advantage of current generic developments introduced for the LHC upgrades: CERN GLIB boards...
Lorne Levinson
(Weizmann Institute of Science (IL))
9/24/13, 6:19 PM
Poster
The current off-chamber readout chain in the ATLAS experiment consists of sub-detector specific ReadOut Drivers (RODs), typically 9U VME cards, which receive data from a number of front-end links. The RODs build event fragments and forward these via point-to-point links, the Read-Out Links (ROLs) to the ReadOut System (ROS). The functionality of the RODs, not only consisting of fragment...
Rui Gao
(University of Oxford (GB))
9/24/13, 6:20 PM
Poster
The TORCH detector is proposed for the low-momentum particle identification upgrade of the LHCb experiment. It combines Time-Of-Flight and Cherenkov techniques to achieve positive π/K/p separation up to 10GeV/c. This requires a timing resolution of 70ps for single photons. This paper will report on the electronics developed for such measurements, using commercial Micro Channel Plate devices...
Mikhail Matveev
(Rice University)
9/24/13, 6:25 PM
Poster
We report the results of our efforts in the past year to upgrade the Cathode Strip Chamber (CSC) Muon Sorter at CMS. After presenting an overview of the existing CSC Track Finder hardware and upgrade requirements we describe the modification of the existing board and transition to a new Muon Sorter. Then we discuss the improved sorting algorithm and its inplementation in firmware. Current...
Jamieson Olsen
(Fermilab)
9/24/13, 6:26 PM
Poster
High luminosity conditions at the LHC pose many unique challenges for potential silicon based track trigger systems. Among those challenges is data formatting, where hits from thousands of silicon modules must first be shared and organized into overlapping eta-phi trigger towers. Communication between nodes requires high bandwidth, low latency, and flexible real time data sharing, for which a...
Matthias Gorzellik
(Albert-Ludwigs-Universitaet Freiburg (DE))
9/24/13, 6:27 PM
Poster
The GANDALF framework has been developed to deliver a high precision, high performance detector readout and trigger system for particle-physics-experiments such as the COMPASS-II experiment at CERN. Combining the high performance pulse digitization and feature extraction capabilities of twelve GANDALF modules, each comprising a Virtex-5 SX95T, with the strong computation power of a Virtex-6...
200.
NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs.
Alessandro Lonardo
(Universita e INFN, Roma I (IT))
9/24/13, 6:28 PM
Poster
The adoption of GPUs in the low level trigger systems is currently being investigated in several HEP experiments.
While GPUs show a deterministic behaviour in performing computational
tasks, data communication is the main source of fluctuations in the response time of such systems.
We designed NaNet, a FPGA-based NIC supporting 1/10GbE links and the custom 34 Gbps APElink channel.
The...
Andrea Baschirotto
(University of Milan-Bicocca)
9/25/13, 9:00 AM
Oral
The CMOS nanometer technologies represent a key opportunity for performance improvements, in terms of signal processing quality, power and area, but at the same time is an exciting challenge for analog designers to face MOS second-order effects present in scaled technologies which strongly modifies transistor behavior and operations.
Innovative solutions will be presented to mitigate the...
Marco Ghibaudi
(Scuola Superiore Sant'Anna di Studi Universitari e di Perfezion)
9/25/13, 9:50 AM
Oral
The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu.
We present the hardware and FPGA firmware...
Cristian Alejandro Fuentes Rojas
(CERN)
9/25/13, 10:15 AM
The precision requirements of the vertex detector at CLIC impose strong limitations on the mass of such a detector (<0.2% of X0 per layer). To achieve such a low mass, ultra-thin hybrid pixel detectors are foreseen, while the mass for cooling and services will be reduced by implementing a power-pulsing scheme that takes advantage of the low duty cycle of the accelerator. The principal aim is...
Marian Krivda
(University of Birmingham (GB))
9/25/13, 10:15 AM
Oral
After three years of successful operation of Alice Central Trigger Processor (CTP) system for proton-proton, Pb-Pb and p-Pb collisions, the Alice CTP is going to be upgraded with a new L0 board in order to improve the performance of the Alice trigger system. The new L0 board will include several new features: an additional trigger level "LM", which will precede the L0 trigger and will improve...
Dr
Andrew William Rose
(Imperial College Sci., Tech. & Med. (GB))
9/25/13, 11:10 AM
The LHC will restart in 2015 with a higher centre-of-mass energy and luminosity. To allow the CMS physics programme to fully exploit these increases the CMS Level-1 trigger must maintain similar efficiencies for searches and precision measurements to those achieved in 2012. With an average of 50 interactions occurring in each bunch-crossing, it will be challenging to select interesting physics...
Helio Takai
(Brookhaven National Laboratory (US))
9/25/13, 11:35 AM
The ATLAS LAr calorimeters plan to upgrade the readout electronics for both Phase-I and Phase-II LHC luminosity upgrades. Detector signals will be digitized at the front-end, and data will be streamed out to the back-end system continuously. Therefore, radiation tolerant ADCs are key components for both upgrade phases.
This presentation will report on irradiation test results of...
Pawel Piotr Plucinski
(Stockholm University (SE))
9/25/13, 11:35 AM
In 2015 the Large Hadron Collider will run with increased center-of-mass energy and luminosity. To maintain trigger efficiency against increased pileup rates, event topology information will be added to the ATLAS Level-1 real time data path and processed by a new Topology Processor (L1Topo). In phase-I, a new digital readout for the Liquid Argon calorimeters will provide finer granularity and...
Alexander Madorsky
(University of Florida (US))
9/25/13, 12:00 PM
Oral
One of the workhorses for the CMS Level-1 Muon Trigger upgrade is the Muon Trackfinder board with a Virtex-7 generation FPGA (MTF7). Optimized to handle large input bandwidth for data from the different muon sub-detectors, the board also has 1 Gigabyte of fast access memory to be used as a look-up table while assigning muon momenta. We discuss the challenges and solutions for implementing the...
Marco Fornasari
(Avago Technologies)
9/25/13, 2:00 PM
Oral
Parallel optics modules are complex hybrid solutions that incorporate chip design of the VCSEL and PIN arrays plus optics design of the lens; a packaging design to provide thermal management and environmental protection; and an electrical subassembly that includes the IC and firmware. All of this needs to be designed to operate reliably over a long lifetime at worse case conditions. This is...
Chengxin Zhao
(University of Oslo (NO))
9/25/13, 2:50 PM
Oral
This paper will discuss the performance of the PHOS level-0 trigger and planned improvements for RUN 2. Due to hardware constraints the Trigger Region Unit boards are limited to an operating frequency of 20 MHz. This has led to some ambiguity and biases of the trigger inputs. The trigger input generation scheme was therefore optimized to improve the performance. Proposed actions to further...
Guido Volpi
(Istituto Nazionale Fisica Nucleare (IT))
9/25/13, 3:15 PM
The ATLAS Fast TracKer is a custom electronics system that will operate at the full Level-1 accept rate, 100 kHz, to provide high quality tracks as input to the Level-2 trigger. The event reconstruction is performed in hardware, thanks to the massive parallelism of associative memories (AM) and FPGAs. We present the advantages for the physics goals of the ATLAS experiment and the recent...
Sergei Lusin
(University of Wisconsin (US))
9/25/13, 3:15 PM
The global design process of high-energy physics experiments typically follows three overlapping stages consisting of detector modeling, detector integration and services implementation phases.
This process sometimes results in unexpected interactions between subsystems. At the CMS experiment at CERN we have had over two years of operational experience during which time we have observed...
Bruno Angelucci
(Sezione di Pisa (IT))
9/25/13, 3:40 PM
The main goal of the NA62 experiment at CERN is to measure the branching ratio of the ultra-rare K+ → π+νν decay, collecting about 100 events to test the Standard Model of Particle Physics. Readout uniformity of sub-detectors, scalability, efficient online selection and lossless high rate readout are key issues. The TDCB and TEL62 boards are the common blocks of the NA62 TDAQ system. TDCBs...
Krzysztof Piotr Swientek
(AGH University of Science and Technology (PL))
9/25/13, 4:35 PM
Poster
The LHCb detector, operating at the LHC proton-proton collider, has finished its Run I period. After more than two years of collision data taking the experiment accumulated corresponding integrated luminosity of around 3.1 fb-1. The full recorded data sample will be used by physicsts to search for New Physics and precise measurement of CP-violation in heavy flavor quark sector. Despite its...
Tuomas Sakari Poikela
(University of Turku (FI))
9/25/13, 4:36 PM
Poster
In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256x256 pixels with a pixel pitch of 55um.
The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured...
Filip Francis Tavernier
(CERN)
9/25/13, 4:37 PM
Poster
A clock and data recovery IP, the eCDR, is presented which is intended to be implemented on the detector front-end ASICs that need to communicate with the GBTX by means of e-links. The programmable CDR accepts data at 40, 80, 160 or 320 Mbit/s and generates retimed data as well as 40, 80, 160 and 320 MHz clocks that are aligned to the retimed data. Moreover, all the outputs have a programmable...
Tobias Harion
(Kirchhoff-Institut Heidelberg)
9/25/13, 4:38 PM
Poster
KLauS is an ASIC produced in the AMS 350nm SiGe process to read out the charge signals from silicon photomultipliers.
Developed as an analog frontend for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration,
the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with a high precision.
In order to...
Samuel Pierre Manen
(Univ. Blaise Pascal Clermont-Fe. II (FR))
9/25/13, 4:39 PM
Poster
The ALICE Collaboration at the CERN-LHC has
started a vast program of upgrades of the detector in the context
of the increase of the luminosity of the LHC from 2018 on. The
present very front-end electronics (VFE) of the Muon Trigger,
whose acronym is ADULT, must be replaced to limit the aging
of the Resistive Plate Chambers (RPCs) in the future expected
operating conditions. For this...
Piotr Kapusta
(Institute of Nuclear Physics PAN, Krakow (PL))
9/25/13, 4:41 PM
Poster
We present the prototype pixel detector built in the Silicon on Insulator (SOI) technology. The sensor matrix contains 1024 integrating type cells, read continuously out as a serial analog signal. The pixels are protected from the back-gate effect by the Buried P-Well implantations. Measured ENC value was found to be 130 electrons at 100us integration time. An on-chip prototype SAR ADC and a...
Philipp Schwegler
(Max-Planck-Institut fuer Physik (Werner-Heisenberg-Institut) (D)
9/25/13, 4:42 PM
Poster
New ATLAS Monitored Drift Tube (MDT) chambers with reduced tube diameter (sMDT) - 15 mm instead of 30 mm - have been developed for LHC luminosity upgrades. The shorter lengths of the pulse trains due to the smaller tube diameter allow to operate the sMDTs at much higher rates, however the gain in efficiency is limited by the shaping scheme of the current ASD (Amplifier-Shaper-Discriminator)...
Eva Vilella-Figueras
(Universitat de Barcelona)
9/25/13, 4:44 PM
Poster
A monolithical GAPD (Geiger-mode Avalanche PhotoDiode) detector aimed to particle tracking at future linear colliders is being developed. A first prototype of a bidimensional GAPD pixel array has been designed and fabricated with a conventional 0.35 µm HV-CMOS process. The experimental characterization of the device shows that the expected noise counts generated by the sensor can be reduced to...
Andreas Neiser
(Institute of Nuclear Physics, Mainz - Germany)
9/25/13, 4:55 PM
Poster
The TRB3 features four FPGA-based TDCs with <20ps RMS time precision
between two channels and 256+4+4 channels in total. One central FPGA
provides flexible trigger functionality and GbE connectivity including
powerful slow control. We present recent users' applications of this
platform following the COME&KISS principle: Successful test beamtimes
at CERN (CBM), in Juelich and Mainz with an...
Sven Schatral
(University of Heidelberg)
9/25/13, 4:58 PM
Poster
The Compressed Baryonic Matter experiment at FAIR in Darmstadt has special requirements on the Data Acquisition Network. One of them is deterministic latency of all links from the back-end to the front-end, which enables synchronization in the whole read-out tree. Since front-end electronics (FEE) contains mixed-signal circuits for processing of detector raw data, special ASICs were developed....
Paolo De Remigis
(INFN)
9/25/13, 5:09 PM
Poster
The upgrade of the second level electronics of the muon Drift Tube (DT) in CMS is focused on improving the electronic system to maintain its reliability at High Luminosity LHC. The project foresees the relocation of the Sector Collector electronics from the CMS cavern to the counting room. The system requires an electrical to optical conversion operated by the Copper to Optical Fibre (CUOF)...
Rainer Schwemmer
(CERN)
9/25/13, 5:10 PM
Poster
The LHCb experiment will upgrade its DAQ system to a trigger less, 40MHz read-out after LS2. To be able to process the approximately 40Tbit/s of data we will require a massive computing farm. This computing farm can not be installed underground, in the vicinity of the detector anymore due to the enormous power and cooling requirements. An affordable data transport solution has to be found to...
Jingbo Ye
(Southern Methodist University (US))
9/25/13, 5:11 PM
Poster
The integration of VCSEL array and driving ASICs in a custom optical transmitter module (ATx) for operation in the detector front-end is demonstrated. The ATx provides 12 parallel channels with each channel operating at 10 Gbps. The assembly comprises a ceramic substrate with high-density wiring for electrical interface, OE components, and a micro-lens array with guiding structure for optical...
Alfonso Tarazona Martinez
(Valencia Polytechnic University (ES))
9/25/13, 5:13 PM
Poster
Upgrades of the LHC detectors target significantly higher event rates and higher bandwidth over custom links which transmit data, trigger, clock and control (DTCC) between the front-end and the readout units. We report on a DTCC point-to-point link protocol designed to work over 8B/10B encoding with 2 or 4 pair copper implementation or over optical fiber. A version of the DTCC protocol over...
Ludovic Eraud
(LPSC,Centre National de la Recherche Scientifique (FR))
9/25/13, 5:24 PM
Poster
Abstract :
The environment conditions of the Long Duration Balloon flight are the worst possible for high voltage electronics which must survive at the altitude of 40km and a pressure of 5mbar in the Payload of the CREAM (COSMIC Ray Energy And Mass) balloon. Three different high voltage power supplies (1400V, 2000V and 12000V with a maximum consumption of 20 mA per module) were developed at...
A A Hasib
(University of Oklahoma (US))
9/25/13, 5:25 PM
High common mode offset voltages can arise in the ATLAS Pixel detector module communication links that could prevent new Pixel Detector modules from taking data because of the present grounding and power supply schemes. Isolation of all the detector module electronics supply channels eliminates this risk. We propose that it is possible to provide inexpensive, reliable and serviceable power...
Stefano Venditti
(Sezione di Pisa (IT))
9/25/13, 5:36 PM
Poster
The NA62 experiment at the CERN SPS (Super Proton Synchrotron) accelerator aims at studying ultra-rare kaon decays. The high resolution Liquid Krypton (LKr) calorimeter, built for the NA48 experiment, is a crucial part of the NA62 photon-veto system. However, the back-end electronics of the LKr calorimeter has to be redone in order to accommodate the new requirements. The exhaustive...
Gary Drake
(Argonne National Laboratory (US))
9/25/13, 5:37 PM
Poster
The CMS Hadron Calorimeter (HCAL) is scheduled to be upgraded to increase longitudinal depth segmentation in the Barrel and Endcap regions and to improve anomalous signal rejection efficiency in the Forward Region. In order to achieve these goals, the phototransducers and the front-end and back-end electronics of the HCAL will be upgraded in stages over the next several years. New PMTs in...
Nikolaos Trikoupis
(CERN)
9/25/13, 5:49 PM
Poster
For the next LHC run it is required to install 200 W of heating capacity to regenerate the beam screen by desorption of gas trapped on its walls. In the LHC, there are 272 beam screen heaters and the associated electronics limits the heating capacity to 25 W. These electronics are mostly installed inside the LHC tunnel and exposed to its radiation environment.
This paper describes the basic...
Johan Alme
(Department of Physics and Technology)
9/25/13, 5:51 PM
Poster
This paper will present and discuss measurement results of single event upsets in the readout control FPGA of the ALICE Time Projection Chamber during the first LHC running period. The measurements have been performed during stable beam conditions for proton-proton, proton-lead and lead-lead collisions.
William Vigano
(CERN)
9/25/13, 6:01 PM
Poster
A wide range current digitizer card is needed for the acquisition module of the beam loss monitoring systems in the CERN Injector Complex. The fully differential frequency converter allows measuring positive and negative input currents with a resolution of 31nA in an integration window of 2µs. Increasing the integration window, the dynamic range covers 2•1010 were the upper part of the range...
Matevz Cerv
(CERN)
9/25/13, 6:02 PM
Poster
The Diamond Beam Monitor (DBM) is a pCVD diamond pixel tracker for detecting high-energy charged particles. It is planned to be installed in the ATLAS experiment at CERN for the luminosity measurements. In this talk, the overview of the DBM system and the operation of the diamond pixel sensors are described.
Gregory Pigny
(CERN)
9/25/13, 6:03 PM
Poster
The 26 km of vacuum chambers where circulates the beam of LHC (Large Hadron Collider) must be maintained under UHV (Ultra High Vacuum) to minimize the beam interaction with residual gases, and allow the operation of specific systems. The vacuum is measured by several thousands of gauges along the accelerator. Bad vacuum measurements may trigger a beam dump and close the associated sector...
Fernando Carrio Argos
(Universidad de Valencia (ES))
9/25/13, 6:04 PM
Poster
The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux...
Eric Shearer Hazen
(Boston University (US))
9/25/13, 6:05 PM
Poster
The AMC13 provides clock, timing and DAQ service for many subdetectors
and central systems in the upgraded CMS detector. This year we have
developed an upgraded module, the AMC13XG, which supports 10 gigabit
optical fiber and backplane interfaces. Many of these modules are now
being installed in the CMS experiment during the current LHC shutdown.
We describe the implementation using...
Peyton Rose
(University of California,Santa Cruz (US))
9/25/13, 6:06 PM
Poster
In the event of beam loss at the LHC, ATLAS inner detector components nearest the beamline may be subjected to unusually large amounts of radiation. Understanding their behavior in such an event is important in determining whether they would still function properly. We built a SPICE model of the silicon strip module electrical system to determine the behavior of its elements during a realistic...
Thierry Caceres
(LAL Orsay)
9/25/13, 6:07 PM
Poster
A complex readout electronic chain has been designed for the EUSO-Balloon project. It contains two elements: the EC units (9 of them) and the EC-ASIC boards (6). The EC unit includes 64-channel Multi-Anode Photomultipliers and a set of pcbs used to supply the 14 different high voltages needed by the MAPMTs and to read out the analog output signals. These signals are transmitted to the EC-ASIC...
94.
Performance evaluation of multiple (16 channels) sub-nanosecond TDC implemented in low-cost FPGA
Georgios Konstantinou
(National Technical Univ. of Athens (GR))
9/25/13, 6:08 PM
Poster
NA62 experiment Straw tracker frontend board serves as a gas-tight detector cover and integrates two CARIOCA chips, a low cost FPGA (Cyclon III, Altera) and a set of 400Mbit/s links to the backend. The FPGA houses 16 sub-nanosecond resolution TDCs with derandomizers and an output link serializer. Evaluation methods, including simulations, and performance results of the system in the lab and on...
Juan Mauricio Ferre
(University of Barcelona (ES))
9/25/13, 6:09 PM
Poster
The LHCb collaboration foresees a major upgrade of the detector for the high luminosity run that should take place after 2018. Apart from the increase of the instantaneous luminosity at the interaction point of the experiment, one of the major ingredients of this upgrade is a full readout at 40MHz of the sub-detectors and the acquisition of the data by a large farm of PC. The trigger will be...
Jay Chapman
(University of Michigan, Ann Arbor, Michigan, 48109, USA)
9/25/13, 6:21 PM
Poster
A Verilog Behavioral simulation of sTGC trigger will be presented based on the current baseline concept with particular focus on the Level 1 latency obtained. Data for this trigger is taken from detector simulations with Garfield and PSpice, current measurements made in the existing small wheel, and FLUGG simulation of the arrival times of hits at high luminosities. These simulations will...
Dinyar Rabady
(University of Vienna (AT))
9/25/13, 6:22 PM
Poster
To continue triggering with the current performance in the LHC Run 2 the Global Muon Trigger (GMT) of the CMS experiment will be reimplemented in a Virtex-7 card utilizing the uTCA architecture. The thus available high-capacity input as well as increased logic could be used to migrate the final sorting stage of each subsystem to the GMT. Additionally the GMT will calculate a muon’s isolation...
Rafael Ballabriga Sune
(CERN)
9/26/13, 9:00 AM
Oral
This contribution will review on-going ASIC developments taking place within the context of the Medipix3 Collaboration and also discuss a development aimed at a future CLIC vertex detector.
We will begin with a description of the Medipix3RX ASIC and its innovative architecture. The measurement results and the lessons learned in the project will be covered in detail. We will discuss the novel...
Jingbo Ye
(Southern Methodist University, Department of Physics)
9/26/13, 9:50 AM
A VCSEL driver has been designed and fabricated in a SMIC 65-nm CMOS process. The preliminary testing results show the ASIC can work at 10 Gbps without peaking or emphasis structures. Due to the thin gate oxide of the technology and large size transistors used in the design, the VCSEL driver is potential radiation tolerant. We will present the irradiation testing results in the conference. To...
Davide Braga
(STFC - Science & Technology Facilities Council (GB))
9/26/13, 9:50 AM
Oral
The CMS Binary Chip 2 (CBC2) is a full-scale prototype ASIC developed for the front-end readout of the high-luminosity upgrade of the CMS silicon strip Tracker. The 254-channel, 130nm CMOS ASIC is designed for the binary readout of double-layer modules, and features cluster-width discrimination and coincidence logic for detecting high-PT track candidates. The chip was manufactured in January...
Xiaoting Li
(Central China Normal University, Southern Methodist University)
9/26/13, 10:15 AM
We present several ASICs of optical data transmission for the ATLAS liquid argon calorimeter trigger upgrade. These ASICs include a two-channel serializer (LOCs2), a single-channel and a four-channel VCSEL driver (LOCld1 and LOCld4), each channel operating at 8 Gbps. The serializer ASIC implements a low-latency, low-overhead, quick-resynchronization interface chip (LOCic) between ADCs and...
Dominik Wladyslaw Przyborowski
(AGH University of Science and Technology (PL))
9/26/13, 10:15 AM
Oral
The design and measurements of front--end electronics for straw tubes tracker (STT) at PANDA experiment are presented. The challenges for front--end electronics are discussed and the proposed architecture comprising switched gain preamplifier, pole--zero cancellation circuit (PZC), variable peaking time shaper, ion tail cancellation circuit (TC) and baseline holder (BLH) is described. The...
Anthony Weidberg
(University of Oxford (GB))
9/26/13, 11:10 AM
Single Event Upsets (SEU) are expected to occur during high luminosity running of the ATLAS SemiConductor Tracker (SCT). The SEU cross sections were measured in pion beams with momenta in the range 200 to 465 MeV/c and proton test beams at 24 GeV/c but the extrapolation to LHC conditions is non-trivial because of the range of particle types and momenta. The SEUs studied occur in the p-i-n...
Michael Krieger
(University of Heidelberg)
9/26/13, 11:10 AM
Oral
For the readout of the transition radiation detectors of the upcoming CBM experiment at FAIR, a self-triggered multi-channel mixed signal ASIC for signal amplification, digitization, and processing is under development.
The SPADIC 1.0 chip has 32 channels, each composed of a charge sensitive amplifier, a 9 bit pipelined ADC continuously running at 25 MHz sampling rate and a programmable...
Jessica Metcalfe
(Brookhaven National Laboratory (US))
9/26/13, 11:35 AM
Oral
Measurements of the first prototype VMM1 ASIC designed at Brookhaven National Laboratory in 130 nm CMOS and fabricated in spring 2012 are presented. The 64-channel ASIC features a novel design for use with several types of micropattern gas detectors. The data driven system measures peak amplitude and timing information in tracking mode including sub-threshold neighbors and first channel hit...
Lauri Juhani Olantera
(CERN)
9/26/13, 11:35 AM
Hollow-core photonic-bandgap fibres (HC-PBGFs) offer many advantages over conventional fibres, such as low latency and radiation hardness; properties that make HC-PBGFs interesting for the HEP community. This contribution presents the results of gamma irradiation tests carried out using a new type of HC-PBGFs that combines low enough attenuation over distances that are reasonable for HEP...
Gary Drake
(Argonne National Laboratory)
9/26/13, 12:00 PM
Oral
We present results on a new version of the QIE (Charge Integrating Encoder), a custom Application Specific Integrated Circuit (ASIC) designed at Fermilab. Developed specifically for the measurement of charge from detectors in high-rate environments, this most recent addition to the QIE family features 3 fC sensitivity, 17-bits of dynamic range with logarithmic response, a Time-to-Digital...
Helio Takai
(Brookhaven National Laboratory (US))
9/26/13, 2:50 PM
There is great interest in using Field Programmable Gate Arrays (FPGAs) within high-energy physics experiments due to their reconfigurability, ease of use, and support for high-speed serial I/O. SRAM-based FPGAs, however, are susceptible to radiation induced single event upsets. This paper estimates the soft-error upset rate of the Kintex-7 FPGA within the ATLAS Liquid Argon Calorimeter...
Herve Marie Xavier Grabas
(CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
9/26/13, 3:15 PM
Oral
SamPic0 is a Time and Waveform to Digital Converter (TWDC) multichannel chip. Each of its 16 channels associates a DLL-based TDC providing a raw time with an ultra-fast analogue memory allowing fine timing extraction as well as other parameters of the pulse. Each channel also integrates a discriminator that can trigger it independently or participate to a more complex trigger. After...
Nathalie Seguin-Moreau
(U)
9/26/13, 3:40 PM
Oral
Imaging calorimetry at the International Linear Collider requires highly granular and innovative detectors. Technological prototypes have been built and tested under the CALICE collaboration framework and FP6 EUDET, FP7 AIDA EU programs. These prototypes are readout by multi-channel chips named SKIROC2, SPIROC2 and HARDROC2, designed in SiGe 350 nm technology by the IN2P3 OMEGA group.
In...
Marek Penno
(Deutsches Elektronen-Synchrotron (DE))
9/26/13, 4:05 PM
The Real-time Histogramming Unit (RHU) is a VME board for sampling and processing discriminated signals from detectors in real time and free of dead-time. The RHU is used at the CMS experiment to measure the arrival time of signals from the BCM1F detectors relative to the orbit trigger of the LHC at CERN. The RHU incorporates a FPGA, 21MBit memory and an embedded Linux system for readout. For...
Vincent Bobillier
(CERN)
9/26/13, 5:00 PM
Filip Francis Tavernier
(CERN)
9/26/13, 5:00 PM
Kostas Kloukinas
(CERN)
9/26/13, 5:00 PM
Jean-Pierre Cachemiche
(Centre National de la Recherche Scientifique (FR))
9/26/13, 5:00 PM
Oral
Sandro Bonacini
(CERN)
9/26/13, 5:15 PM
Andrew William Rose
(Imperial College Sci., Tech. & Med. (GB))
9/26/13, 5:20 PM
Oral
Matteo Di Cosmo
(Ministere des affaires etrangeres et europeennes (FR))
9/26/13, 5:20 PM
Isaac Troyano Pujadas
(CERN)
9/26/13, 5:40 PM
Oral
Jingbo Ye
(Southern Methodist University, Department of Physics)
9/26/13, 5:40 PM
Fernando Carrio Argos
(Universidad de Valencia (ES))
9/26/13, 5:50 PM
Jingbo Ye
(Southern Methodist University, Department of Physics)
9/26/13, 6:00 PM
Jean-Pierre Cachemiche
(Centre National de la Recherche Scientifique (FR))
9/26/13, 6:05 PM
Alexander Paramonov
(Argonne National Laboratory (US))
9/26/13, 6:20 PM
Eric Shearer Hazen
(Boston University (US))
9/26/13, 6:25 PM
Sarah Seif El Nasr
(University of Bristol (GB))
9/26/13, 6:30 PM
Yann Lamy
(CEA- LETI)
9/27/13, 9:00 AM
Oral
After a tremendous technology modules development phase, 3D integration is now looking for the right use cases. Miniaturization and bandwidth needs are partially addressed by 2,5D heterogeneous interposers, but with limited impacts on competitiveness and cost. Disruptive 3DIC stacking is potentially offering unmatched performances and scalability in both niche and consumers markets but is...
Kambiz Mahboubi
(Physikalisches Institut, Universitaet Freiburg)
9/27/13, 11:05 AM
For the HL-LHC, ATLAS will install a new all-silicon tracking system. The strip part will comprise five barrel layers and seven end caps on each side. The detectors will be connected to highly-integrated low-mass front-end electronic hybrids with custom-made ASICs in 130nm technology. The hybrids are flexible PCB four-layer copper polyimide constructions. They are designed and populated at the...
Wojciech Dulinski
(Institut Pluridisciplinaire Hubert Curien (FR))
9/27/13, 11:30 AM
Monolithic CMOS Pixels (MAPS) integrate on the same silicon substrate the radiation sensor element with the processing electronics.
Their thickness can be very small: typically less than 50 µm. This allows for very small material budget, if not spoiled by other mechanics elements. In order to demonstrate feasibility of large area, ultra-light sensor ladders (< 0.1% radiation length) based on...
