TWEPP 2013 - Topical Workshop on Electronics for Particle Physics

Europe/Zurich
Perugia, IT

Perugia, IT

<font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
Jorgen Christiansen (CERN) , Philippe Farthouat (CERN)
Description

The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.

LHC experiments (and their operational experience) will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.

The purpose of the workshop is :

- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities

- to review the status of electronics for the LHC experiments

- to identify and encourage common efforts for the development of electronics

- to promote information exchange and collaboration in the relevant engineering and physics communities.



 

Support
    • Welcome Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy

      TWEPP Opening

      Convener: Gian Mario Bilei (Universita e INFN (IT))
      • 1
        TWEPP Opening
        Speaker: Philippe Farthouat (CERN)
        Slides
      • 2
        Welcome from the Local Organizing Committee
        Speaker: Gian Mario Bilei (Universita e INFN (IT))
        Slides
      • 3
        Welcome from Director of INFN Perugia and Director of Department of Physics
        Speaker: Prof. Giancarlo Mantovani (INFN)
    • Opening 1 Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Gian Mario Bilei (Universita e INFN (IT))
      • 4
        Electronics for Particle Physics in Perugia
        This presentation will try to give an overview of the electronics developments, related to the particle physics experiments, carried out in Perugia within the framework of a two decades collaboration between the INFN and the University of Perugia. In particular, will be addressed the recent and future activities in CMS, e.g. the future 65nm pixel chip read-out and the track/trigger system, the NA48 and NA62 trigger system, the AMS power supply system and the R&D activities related to 3D VLSI electronics and silicon on diamond devices.
        Speaker: Daniele Passeri
        Slides
    • 4:30 PM
      Break
    • Opening 2 Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Philippe Farthouat (CERN)
      • 6
        Carbon nanotubes and graphene nanoribbons for future IC interconnect technology
        Given their physical limits, conventional materials such as copper are expected to fail in meeting many of the requirements for future nanoscale IC interconnects. Due to their outstanding electrical, thermal and mechanical properties, Carbon Nanotubes (CNTs) or Graphene Nano-Ribbons (GNRs) are proposed as innovative interconnect materials. This presentation will first discuss the first examples of real-world successful integration between such interconnects and CMOS technologies. Then, a simple transmission line model will be presented, to describe the electrical propagation along CNT or GNR interconnects, derived from a semi-classical electrodynamical model. Referring to the nanointerconnects predicted for the 22nm and 16 nm technology at chip and package level, a performance comparison will be carried out between copper, CNT, GNR and hybrid solutions.
        Speaker: Antonio Maffucci (University of Cassino and Southern Lazio)
        Slides
      • 7
        The First Long Shutdown (LS1) and future upgrades of the LHC machine
        The LHC has been delivering data to the physics experiments since the first collisions in 2009. The first long shutdown (LS1), which started on 14 February 2013, was triggered by the need to consolidate the magnet interconnections so as to allow the LHC to operate at the design energy of 14 TeV in the centre-of-mass for proton–proton collisions. It has now become a major shutdown that, in addition, includes other repairs, consolidation, upgrades and cabling across the whole accelerator complex and the associated experimental facilities. LHC physics will resume in early 2015 while the other injectors and experimental areas of CERN will resume their operation in the second half of 2014. The presentation first will describe the main activities of the LS1 and the operation strategy up to the LS2. Then, it will give the plans for the full exploitation of the LHC in line with the Update of the European Strategy for Particle Physics.
        Speaker: Frederick Bordry (CERN)
        Slides
    • Welcome Reception in the Cloister of San Lorenzo Cathedral
    • Plenary 1: Space Application Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Jorgen Christiansen (CERN)
      • 8
        The Design of the Alphasat Payload Processor - Advancing Space Electronics!
        Alphasat is the most sophisticated and largest European telecommunication satellite ever built allowing Inmarsat to offer flexible communications to maritime, aeronautical and other mobile customers. Alphasat supports over400 spot beams processing more than 750 simultaneous channels in L-band. This presentation will share some of the key technical challenges encountered during the design of the Alphasat Payload Processor - many of the technologies used on this project simply did not exist when the original proposal was drafted. The beamforming DSP provides unprecedented flexibility and operational capability in terms of routing, channelization and combining channels to the desired beam.
        Speaker: Rajan BEDI
        Slides
    • ASICs: A1a Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Marcus Julian French (STFC - Science & Technology Facilities Council (GB))
      • 9
        Development of variable sampling rate, low power 10-bit SAR ADC in 130 nm IBM technology
        The design and preliminary measurements results of 10-bit Successive Approximation Register (SAR) Analog to Digital (ADC) converter are presented. The prototype of the SAR ADC was designed and fabricated in 130 nm IBM technology. Preliminary measurements show that the ASIC is functional and the obtained ENOB (effective number of bits) is of about 9.2 bits. Power consumption of the ADC is around 1.1 mW per channel at nominal sample rate 40 MS/s. Maximum sampling frequency is around 50 MHz.
        Speaker: Jakub Moron (AGH University of Science and Technology (PL))
      • 10
        A multichannel Time-to-Digital Converter ASIC with better than 3 ps-rms time resolution
        The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than +/- 0.9 LSB and differential-non-linearity (INL) of better than +/- 1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology.
        Speaker: Jorgen Christiansen (CERN)
        Paper
        Slides
    • Systems, Planning, Installation, Commissioning and Running Experience: B1a
      Convener: Ken Wyllie (CERN)
      • 11
        Evaluation results of xTCA equipment for HEP experiments at CERN
        The MicroTCA and AdvancedTCA industry standards are candidate platforms for modular electronics for the upgrade of the current generation of high energy physics experiments. The PH-ESE group at CERN launched in 2011 the xTCA evaluation project with the aim of performing technical evaluations and eventually providing support for commercially available components. Different devices from different vendors have been acquired, evaluated and interoperability tests have been performed. This paper presents the test procedures and facilities that have been developed and focus is given to the evaluation results including electrical, thermal and interoperability aspects.
        Speaker: Matteo Di Cosmo (Ministere des affaires etrangeres et europeennes (FR))
        Paper
        Slides
      • 12
        A GLIB-based uTCA demonstration system for HEP experiments
        The Gigabit Link Interface Board (GLIB) project is an FPGA-based platform for users of high-speed optical links in high energy physics (HEP) experiments. The project delivers hardware, firmware/software and documentation as well as provides user support. These resources facilitate the development of evaluation platforms of optical links in the laboratory as well as triggering and/or data acquisition systems in beam or irradiation tests of detector modules. This article focuses on the demonstration of a triggering and data acquisition setup for HEP experiments using hardware and firmware/software resources provided by the GLIB project.
        Speaker: Manoel Barros Marin (CERN)
        Paper
        Slides
    • 10:40 AM
      Break
    • ASICs: A1b Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Marcus Julian French (STFC - Science & Technology Facilities Council (GB))
      • 13
        Pixel front-end development in 65 nm CMOS technology
        Upgrade of luminosity of the LHC (HL-LHC) imposes severe constraints on detector tracking systems in terms of radiation hardness and ability to cope with high hit rates. One possible way of keeping track with increasing luminosity is usage of more advanced technologies. Ultra deep sub-micron CMOS technology allows design of complex and high speed electronics with high integration density. In addition these technologies are inherently radiation hard. We present a prototype of analog pixel front-end designed in 65 nm CMOS technology with applications oriented to upgrade of the ATLAS Pixel Detector. Aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be presented.
        Speaker: Miroslav Havranek (Universitaet Bonn (DE))
        Paper
        Slides
      • 14
        A 20 mW, 4.8 Gbit/sec, SEU robust serializer in 65nm for read-out of data from LHC experiments
        The availability of a sub 1-W SerDes for future LHC read-out systems is of paramount importance. This work relates to the design of two alternative architectures for the critical serializer block within a SerDes with the objective of achieving a power consumption of less than 30 mW at the operating speed of 4.8 Gbit/sec. Two alternative architectures are implemented using a commercial 65nm LP-CMOS technology. The architectures used are a “simple-TMR” and a “code-protected” one, and are meant to investigate different strategies against SEU effects. While using the same technology and flip-flops, the simple-TMR architecture results in a consumption of 30 mW, the code-protected one of 19 mW, which are better than 1/4 of the power used in state-of-the-art rad-hard serializers. The robustness to SEU effects is also presented.
        Speaker: Daniele Felici (Universita e INFN Roma Tor Vergata (IT))
        Paper
        Slides
      • 15
        Next generation Associative Memory devices for the FTK tracking processor of the ATLAS experiment
        The AMchip is a VLSI device that implements the associative memory function, a special content addressable memory specifically designed for high energy physics applications and first used in the CDF experiment at Tevatron. The 4th generation of AMchip has been developed for the core pattern recognition stage of the Fast TracKer (FTK) processor: a hardware processor for online reconstruction of particle trajectories at the ATLAS experiment at LHC. We present the architecture, design considerations, power consumption and performance measurements of the 4th generation of AMchip. We present also the design innovations toward the 5th generation and the first prototype results.
        Speaker: Matteo Mario Beretta (Istituto Nazionale Fisica Nucleare (IT))
        Paper
        Slides
    • Systems, Planning, Installation, Commissioning and Running Experience: B1b Trumpet 3, Congress Center

      Trumpet 3, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Ken Wyllie (CERN)
      • 16
        High speed readout electronics development for frequency-multiplexed kinetic inductance detector design optimization
        Microwave Kinetic Inductance Detector (MKID) are a promising solution for space-borne mm-wave astronomy. To optimize their design and reduce the impact of the primary Cosmic Rays interaction with the substrate, the phonon propagation in the silicon substrate must be studied. A dedicated fast readout electronics, using channelized Digital Down Conversion for monitoring up to 16 MKIDs over a 100MHz bandwidth was developed. Thanks to the fast ADC sampling and steep digital filtering, In-phase and Quadrature samples, having a high dynamic range, are provided at 2MSPS. This paper describes the technical solution chosen and the results obtained.
        Speaker: Olivier Raymond Bourrion (Centre National de la Recherche Scientifique (FR))
        Paper
        Slides
      • 17
        The proposed trigger-less TBit/s readout for the Mu3e experiment
        The Mu3e experiment searches for charged lepton flavor violation in the rare decay mu->eee with a projected sensitivity of 10^-16. Precise measurement of the decay product momentum, decay vertex and time is necessary for background suppression at rates of 10^9 muons/s. This can be achieved by combining an ultra-lightweight pixel tracker based on HV-MAPS with two timing systems. The trigger-less readout of the detector with three stages of FPGA-boards over multi GBit/s optical links into a GPU filter farm will be presented. In this scheme data from all sub-detectors is merged and distributed in time slices to the filter farm.
        Speaker: Dirk Wiedner (Ruprecht-Karls-Universitaet Heidelberg (DE))
        Paper
        Slides
      • 18
        Upgraded Readout and Digitizing System for the ATLAS Tile Calorimeter Demonstrator
        During the shutdown of the ATLAS scintillating Tile calorimeter (TileCal) in 2013/14 one of its ondetector electronic modules will be replaced with a compatible hybrid module, which also serves as a demonstrator for future upgrades. This is being built to fulfill all requirements for the complete upgrade of the TileCal electronics in 2022 but augmented to stay compatible with the present system. We describe a new Front End Board (FEB) that provides amplification and shaping, a Main Board that handles digitization and a high-speed communication Daughter Board. This system will permit us to acquire experience with a future fully digital readout system without disturbing the current analog trigger system.
        Speaker: Steffen Muschter (Stockholm University)
        Paper
        Slides
    • 12:25 PM
      Lunch
    • Plenary 2: ASIC Technology Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Christophe De La Taille (Inst. Nat. Phys. Nucl. & Particules (FR))
      • 19
        Mismatch in deep-submicron and the consequences for analog designs
        Bandwidth, accuracy and power are the main parameters that connect the world of technology and sensor physics to the digital systems-on-silicon and advanced signal processing. Bandwidth is associated with drive strength, lithography node, and available current. Accuracy relates to static device properties such as device mismatch. Bandwidth and accuracy tend to pose opposing demands on technologies. In this talk a short description of device mismatch is given, the technology trends for mismatch are examined as well as consequences for analog circuitry. As dimensions shrink down to the 22 nanometer level, the impact of these limits becomes more severe and more effort and power are needed to mitigate the problems. Often a smart interaction with the system allows overcoming performance loss. In some systems calibration is an option, however cost and power budgets require that the designer optimally uses the available opportunities of the devices and technology.
        Speaker: Marcel Pelgrom
        Slides
    • ASICs: A2 Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Christophe De La Taille (Inst. Nat. Phys. Nucl. & Particules (FR))
      • 20
        MISTRAL & ASTRAL: Two CMOS Pixel Sensor Architectures dedicated to the Inner Tracking System of the ALICE Experiment
        A detector, equipped with 50 um thin CMOS Pixel Sensors (CPS), is being designed for the upgrade of the Inner Tracking System (ITS) of the ALICE experiment at LHC. Two CPS flavours, MISTRAL and ASTRAL, are being developed at IPHC aiming to meet the requirements of the ITS upgrade. The first is derived from the MIMOSA28 sensor designed for the STAR-PXL detector. The second integrates a discriminator in each pixel to improve the readout speed and power consumption. This paper will describe in details the sensor development and show the preliminary test results.
        Speaker: Frederic Morel (IPHC/CNRS/IN2P3)
        Paper
        Slides
      • 21
        A prototype hybrid pixel detector ASIC for the CLIC experiment
        A prototype hybrid pixel detector ASIC whose design is tuned to the requirements of a vertex detector for CLIC is described and first electrical measurements presented. The chip has been designed using a commercial 65 nm CMOS technology and comprises a matrix of 64 x 64 square pixels each measuring 25 um on the side. The main features include simultaneous 4-bit measurement of Time-over-Threshold (ToT) and Time-of-Arrival (ToA) with 10 ns accuracy, on-chip data compression scheme and power pulsing capability.
        Speaker: Pierpaolo Valerio (CERN)
        Paper
        Slides
      • 22
        Design of the analog front-end for the Timepix3 and Smallpix hybrid pixel detectors in 130nm CMOS technology
        This front-end contains a single-ended preamplifier with a structure for leakage current compensation, suitable to both signal polarities. Preamplifier and discriminator are required to be fast, to allow a Time-of-Arrival measurement with a resolution of 1.56ns. Time-Over-Threshold (TOT) is also measured; the monotonicity of TOT with respect to the input charge is greatly improved as compared to the previous Timepix chip. The analog area is only 55um x 13.5um. The design of the front-end, the main features of the chips and the first measurements are presented.
        Speaker: Massimiliano De Gaspari (CERN)
        Paper
        Slides
      • 23
        Monolithic Active Pixel Sensor Development for the Upgrade of the ALICE Inner Tracking System
        ALICE plans an upgrade of its Inner Tracking System for 2018. The development of a monolithic active pixel sensor for this upgrade is described. The TowerJazz 180 nm CMOS imaging Sensor process has been chosen as it is possible to use full CMOS in the pixel due to the offering of a deep pwell and also to use different starting materials. Several prototypes have already been designed, submitted for fabrication and some of them tested with X-ray sources and particles in a beam. Radiation tolerance up to the ALICE requirements has also been verified.
        Speaker: Walter Snoeys (CERN)
        Paper
        Slides
    • Systems, Planning, Installation, Commissioning and Running Experience: B2 Trumpet 3, Congress Center

      Trumpet 3, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Magnus Hansen (CERN)
      • 24
        Phase-I Upgrade of the Trigger Readout Electronics of the ATLAS Liquid-Argon Calorimeters and the Expected System Performance
        The Phase-I luminosity upgrade of the LHC, planned for 2018, requires an improved trigger performance of the LHC detectors in order to suppress increasing pile-up noise. In the Phase-I upgrade of the read-out electronics of the ATLAS LAr Calorimeters high-granularity signals are provided to the Calorimeter trigger system for improved trigger feature extraction. The general design of the future LAr Calorimeter read-out system is being presented, including the newly developed system components for analog and digital signal processing, and high-bandwidth optical data transmission. Recent results of the simulated system performance for digital signal filtering and trigger feature identification will also be reported.
        Speaker: Johannes Philipp Grohs (Technische Universitaet Dresden (DE))
        Slides
      • 25
        The RCU2 - A Proposed Readout Electronics Consolidation for the ALICE TPC in Run 2
        The RCU2 - A Proposed Readout Electronics Consolidation for the ALICE TPC in Run 2 Author: Johan Alme Bergen University College On behalf of the the ALICE TPC Collaboration This paper presents a proposed optimization of the ALICE TPC readout for running at full energy in the Run 2 period after 2014. During these three years an event readout rate of 400 Hz with a low dead time is envisaged for the ALICE central barrel detectors. A new component, the Readout Control Unit 2 (RCU2), is being designed to increase the present readout rate by a factor of at least 2. The immunity to radiation induced errors will also be significantly improved by the new design.
        Speaker: Johan Alme (Bergen University College (NO))
        Paper
        Slides
      • 26
        The Read-Out Driver (ROD) card for the ATLAS experiment: commissioning for the IBL detector and upgrade studies for the Pixel Layers 1 and 2
        The upgrade of the ATLAS experiment at LHC foresees the insertion of an innermost silicon layer, called Insertable B-layer (IBL). IBL read-out system will be equipped with new electronics. The Readout-Driver card (ROD) is a VME board devoted to data processing, configuration and control. A pre-production batch has been delivered in order to perform tests with instrumented slices of the overall acquisition chain, aiming to finalize strategies for system commissioning. In this contribution both setups and results will be described, as well as preliminary studies on changes in order to adopt the ROD for the ATLAS Pixel Layers 1 and 2.
        Speaker: Riccardo Travaglini (Universita e INFN (IT))
      • 27
        Trigger-less readout architecture for the upgrade of the LHCb experiment at CERN
        The LHCb experiment has proposed an upgrade of its detector in order to collect data at ten times its initial design luminosity. The current readout architecture will be upgraded by removing the existing first-level hardware trigger whose efficiency is limited for hadronic channels at high luminosity. The new readout system will record every LHC bunch crossing and send data to a trigger selection process performed entirely by software running in a computing farm. Therefore, the new readout system must cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and technological challenges of such an upgraded system.
        Speaker: Federico Alessio (CERN)
        Paper
        Slides
    • 4:30 PM
      Break
    • Poster: First Part
      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 28
        Radiation hard programmable delay line for LHCb Calorimeter Upgrade
        This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with a 4ps jitter and 18ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35um technology.
        Speaker: Juan Mauricio Ferre (University of Barcelona (ES))
        Paper
      • 29
        The CLARO-SiGe, a front-end ASIC for precise timing measurements at low power
        The CLARO-SiGe is a prototype ASIC for single photon counting with pixellated photomultipliers, designed to sustain a high counting rate at low power. Each channel is made of a charge amplifier to readout the current pulses on a low impedance node and a discriminator with a settable threshold to count the pulses above threshold. The architecture of the whole channel is differential. The threshold of the discriminator is set through a small current injected through a dummy amplifier, which guarantees the simmetry of the differential configuration. Each channel has two discriminators which can be operated ad different speeds, in order to obtain the highest time resolution on the fast channel, while rejecting crosstalk signals thanks to the slower channel which is less sensisitive to crosstalk. Counting rates up to 40 MHz can be sustained. The overall power consumption is about 1 mW per channel.
        Speaker: Claudio Gotti (INFN and Univ. of Milano Bicocca (IT))
      • 30
        Pixel chip architecture optimization based on a simplified statistical and analytical model
        The technical challenges related to increased collision rates of the LHC will significantly affect detector electronics design. Efficient hit processing is achieved in pixel detectors by grouping pixel chips in regions, which share buffering logic. We present an approach to determine an optimized sharing strategy between pixels, depending on the shape of clustered hits in the detector. Simple statistical models of such shapes have been developed with respect to the position in detector where hits take place. Then the buffering performance of different pixel region configurations has been compared, showing significant improvement from architectures that do not feature pixel grouping.
        Speaker: Elia Conti (Universita e INFN (Perugia, IT))
        Paper
      • 31
        Development of variable frequency, power Phase-Locked Loop (PLL) in 130nm CMOS technology
        The design and measurements results of low power Phase-Locked Loop (PLL) prototype for applications in particle physics detectors readout systems are presented. The PLL fabricated in 130nm IBM technology was designed and simulated for frequency range 10MHz-3.5GHz. Internal voltage controlled oscillator (VCO) should work in 16 frequency ranges/modes, switched either manually or automatically. Preliminary measurements done in frequency range 20MHz-1.6GHz showed that the ASIC is functional and generates proper clock. The PLL power consumption at 1GHz and division factor equal 10 is about 0.6mW. As one of main design goals the automatic VCO mode change was positively verified.
        Speaker: Miroslaw Firlej (AGH University of Science and Technology (PL))
        Paper
        Poster
      • 32
        Development of CMOS Pixel Sensor with digital pixel dedicated to future particle physics experiments
        Two designs of CMOS pixel sensor with in-pixel analog to digital conversion have been prototyped in a 0.18µm CIS process. The first design integrates a discriminator into each pixel within an area of 22×33µm2 in order to meet the requirements of the ALICE-ITS upgrade. The second design features 3-bit charge encoding inside a 35×35µm2 pixel which is motivated by the specification of the outer layers of ILD vertex detector. This work is to validate the concept of in-pixel digitization which offers higher readout speed, lower power consumption and less peripheral surface of active area compared to column-level charge encoding.
        Speaker: Thanh Hung PHAM (CNRS)
        Paper
      • 33
        STiC - A Mixed Mode Silicon-Photomultiplier Readout ASIC for Time-of-Flight Applications
        STiC is a mixed mode readout ASIC for Silicon-Photomultipliers developed in the UMC 180nm CMOS technology. The chip has been designed for the EndoToFPET-US project and aims at providing a high timing resolution to high energy physics and medical imaging applications. The signal is read out and discriminated by a dual threshold method. A low threshold discriminator provides a high precision trigger signal while a linearized time-over-threshold method maintains a good energy resolution. An integrated TDC with 50ps bin size is used to digitize the trigger signals. A 16-channel prototype has been produced and measurements have been performed to quantize the performance of the ASIC.
        Speaker: Tobias Harion (Kirchhoff-Institut Heidelberg)
        Paper
      • 34
        The Charge Pump PLL Clock Generator Designed for the 1.56 ns Bin Size Time-to-Digital Converter Pixel Array of Timepix3 Readout Chip
        Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256 x 256 pixels organized in a square pixel-array with 55um pitch. Oscillators running at 640MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter PLL that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage and temperature variations.
        Speaker: Yunan Fu (Univerisity of Bonn)
        Paper
      • 35
        Radiation-Hardened-By-Design Clocking Circuits in 0.13μm CMOS Technology
        We present single-event-hardened phase-locked loop for structured-ASIC and digital delay-locked loop for DDR2 memory interface applications. The PLL covers a frequency range from 12.5 MHz to 500 MHz with an RMS jitter of 4.7 pS. The DLL operates at 267 MHz and has a phase resolution of 60 pS. Designed in 0.13 µm CMOS technology, the PLL and the DLL are hardened against SEEs for charge injection of 250 fC. The PLL and the DLL consumes 17mW and 22mW of power under 1.5V power supply, respectively.
        Speaker: yang You (Southern Methodist University)
        Paper
        Slides
      • 36
        Test Results of the first 3D-IC Prototype Chip Developed in the Framework of HL-SLHC/ATLAS Hybrid Pixel Upgrade
        To face new challenges brought by the upgrades of the Large Hadron Collider at CERN and of ATLAS pixels detector, for which high spatial resolution, very good signal to noise ratio and high radiation hardness are needed, 3D Integrated Technologies are investigated. Commercial offers of such technologies are only very few and the 3D designer's choice is as a consequence strongly constrained. We present here the test results of the first 3D prototype chip developed in the GlobalFoundries 130 nm chips processed by the Tezzaron Company, submitted within the 3D-IC consortium for which a reliable qualification program was developed. Reliability and influence on the integrated devices behavior of Bond Interface (BI) and Through Silicon Via (TSV) connections, both needed for the 3D integration process, has also been addressed by the tests.
        Speaker: Patrick Pangaud (Centre National de la Recherche Scientifique (FR))
        Paper
      • 37
        Common Read-Out Receiver Card for the ALICE Run2 Upgrade
        The ALICE experiment uses custom FPGA-based computer plug-in cards as interface between the optical readout link and the PC clusters of Data Acquisition (DAQ) and High-Level Trigger (HLT). The previous cards for DAQ and HLT have been developed as independent projects and are now facing similar problems with obsolete major interfaces and limited link speeds. A new common card has been developed to enable the upgrade of the read-out chain towards higher link rates while providing backward compatibility with the current architecture. First prototypes could be tested successfully and showed interest from other collaborations.
        Speaker: Heiko Engel (Johann-Wolfgang-Goethe Univ. (DE))
        Paper
        Poster
      • 38
        FPGA-based, radiation-tolerant on-detector electronics for the upgrade of the LHCb Outer Tracker Detector
        The LHCb experiment studies B-decays at the LHC. The Outer Tracker straw tubes detects charged decay particles. The on-detector electronics will be upgraded to be able to digitize and transmit drift-times at every LHC crossing without the need for a hardware trigger. FPGAs have been preferred to application-specific integrated circuits to implement dead-time free TDCs, able to transmit data volumes of up to 36 Gbits/s per readout unit, including the possibility of performing zero suppression. Extensive irradiation tests have been carried out to validate the usage of field-programmable devices in the hostile environment of the LHCb tracking system.
        Speaker: Wilco Vink (NIKHEF (NL))
        Poster
      • 39
        Use of FPGA Embedded Processors for Fast Cluster Reconstruction in the NA62 Liquid Krypton Electromagnetic Calorimeter
        The NA62 experiment at CERN SPS aims to increase the precision in the measure of the Branching Ratio of the K+->pi+nu nubar decay. The required background suppression level due to the decay K+->pi+pi0 can be achieved, among the others, implementing the photon veto in the angular range [1,10] mrad by using a LKr calorimeter. This paper deals with the implementation of the LKr L0 trigger peak reconstruction algorithm on an FPGA by using a mixed architecture based on soft core embedded processors together with custom VHDL modules This solution allows an efficient and flexible reconstruction of the energy-deposition peak.
        Speaker: Nicola De Simone (INFN Rome)
        Paper
      • 40
        Metrics and Methods for TTC-PON System Characterization
        A new generation FPGA-based Timing-Trigger and Control (TTC) system based on emerging Passive Optical Network (PON) technology is being investigated to potentially replace the existing off-detector TTC system used by the LHC experiments. The new system must deliver trigger and data with low and deterministic latency as well as a recovered bunch clock with picosecond-level jitter. It also offers major improvements over its predecessor: bi-directionality as well as higher capacity. This article focuses on the figures of merit used to characterize the various flavours of TTC-PON system architectures, and on the techniques used to extract them.
        Speaker: Dimitrios Marios Kolotouros (University of Ioannina (GR))
        Paper
      • 41
        A New High-Speed Optical Transceiver For Data Transmission at the LHC Experiments
        We report on the development of a new commercial off-the-shelf optical transceiver as a candidate for the transmission of data from the detector to the counting room for experiments at the Large Hadron Collider (LHC). The device is manufactured by Molex using CMOS integrated silicon photonics developed by Luxtera. A transceiver contains four RX and four TX channels operating at 10 Gbps each, and is packaged in a QSFP+ format. The approach features superb manufacturing costs, power consumption, scalability, and reliability. We present performance measurements, radiation tolerance measurements, and plans for deployment in the ATLAS experiment at the LHC.
        Speaker: Alexander Paramonov (Argonne National Laboratory (US))
        Paper
        Poster
      • 42
        Optical Fibre at HL-LHC
        We present results on all aspects of fibre reliability after exposure to the expected doses at HL-LHC. The results for the cold Radiation Induced Attenuation (RIA) are reviewed. The results of new studies of the effect of radiation on fibre bandwidth and mechanical reliability are presented. The fibre bandwidth was studied using measurements of chromatic dispersion and Differential Mode Delay (DMD). The mechanical reliability was studied using dynamic testing and the quality of the cladding was determined by micro-bending trials. These studies allowed us to qualify one SM fibre for use at HL-LHC.
        Speaker: Todd Brian Huffman (University of Oxford (GB))
        Paper
        Slides
      • 43
        A Small-Footprint, Dual-Channel Optical Transmitter for the High-Luminosity LHC (HL-LHC) Experiments
        We present a small-footprint dual-channel optical transmitter module called MTx for the High-Luminosity LHC experiments. The MTx module consists of two separate commercial transmitter optical sub-assemblies (TOSAs) and a dual-channel laser driver ASIC. We have demonstrated that the module prototypes can operate at 10 Gbps using commercial 10 Gbps laser diode drivers. We are developing an 8 Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC to replace the commercial laser driver used in the current MTx prototypes and three prototype ASICs have been designed and tested. The design and testing results of the module and the ASIC are reported.
        Speaker: Chonghan Liu (Southern Methodist University)
        Paper
        Poster
      • 44
        Neutron Irradiation of Optoelectronic Components for HL-LHC Data Transmission Links
        We report on the results of a radiation test carried out using 20 MeV neutrons on optoelectronic components, such as multi-channel transmitters and Si photonics building blocks, for use in future-data transmission links by experiments at the High-Luminosity LHC.
        Speaker: Sarah Seif El Nasr (University of Bristol (GB))
        Paper
        Slides
      • 45
        A Fast UV-LED QRdriver for Calibration System for SiPM Based Scintillator HCAL Detector
        We report on electronic design of new calibration and monitoring system developed for the scintillator tiles calorimeter (AHCAL) for the ILC. System is based on original fast (3 ns pulsewidth) and precise LED driver called QMB. LED driver uses unique Quasi-Resonant circuit with embedded toroidal inductor. The QR-LED driver creates sinusoidal pulse to drive the LED. It has high dynamic range of precise a few nanosecond pulses. This sinus waveform significantly reduced EMC problems in the detector. System of one UV-LED can illuminates 72 scintillating tiles with SiPM using notched fibres. The system is flexible to all necessary task monitoring and calibration of SiPM detector.
        Speaker: Ivo Polak (Acad. of Sciences of the Czech Rep. (CZ))
        Paper
        Poster
      • 46
        Developments on DC/DC converters for the LHC experiment upgrades
        Prototypes of DC/DC converters were designed and built with the aim of satisfying the foreseen working parameters in the Phase 2 LHC experiments, using both MOSFETs and more recent devices like SiC and GaN transistors. Optimization of their design, based on the comparison between the simulated and measured thermal, electrical and mechanical performance, is in progress, and many improvements are under implementation. Many tens of samples, chosen among the devices commercially available in the three different technologies, Si, SiC and GaN, were electrically characterized and tested under gammas, neutron, proton and heavy ion radiation, also using a combined run method.
        Speaker: Agostino Lanza (INFN Pavia (IT))
        Paper
        Poster
      • 47
        A DC-DC Conversion Powering Scheme for the CMS Phase-1 Pixel Upgrade
        A novel powering scheme based on the DC-DC conversion technique will be exploited to power the CMS Phase-1 pixel detector. DC-DC buck converters for the CMS pixel project have been developed, based on the AMIS5 ASIC by CERN. We will show the performance of these devices, including efficiency and line and load regulation at various temperatures. Reliability studies based on a preseries of 200 DC-DC converters as well as mass production techniques for the inductor and the magnetic shielding will be presented. Results from system tests of the full power chain of the pixel barrel detector will be discussed.
        Speaker: Waclaw Karpinski (Rheinisch-Westfaelische Tech. Hoch. (DE))
        Paper
      • 48
        Quality Assurance and Functionality Tests on Electrical Components during the ATLAS IBL Production
        During the shutdown 2013/14, for the enhancement of the current ATLAS Pixel Detector a fourth layer (Insertable B Layer, IBL) consisting of 14 staves is being built and will be installed between the innermost layer and a new beam pipe. A new read out chip generation has been developed and two different sensor designs, a rather conventional planar and a 3D design, have been flip chipped to these front ends. New staves and module flex circuits have been developed as well. Therefore, a production QA test bench has been established to test all production staves before integration with the new beam pipe. Quality assurance measurements under cleanroom conditions, including temperature and humidity control, are performed on the individual components during the various production steps of the IBL, namely connectivity as well as electrical tests and signal probing on individual parts and assembled subsystems. The pre-assembly QC procedures, the capabilities of the stave qualification setup, and recent results from stave testing are presented and discussed.
        Speaker: Ahmed Bassalat (Universite de Paris-Sud 11 (FR))
        Paper
      • 49
        Single-event upset tests on the readout electronics for the pixel detectors of the PANDA experiment.
        The Silicon Pixel Detector (SPD) of the PANDA experiment is the closest one to the interaction point and therefore the sensor and its electronics are the most exposed to radiation. The Total Ionizing Dose (TID) issue has been addressed by the use of a deep-submicron technology (CMOS 0.13 um) for the readout ASICs. While these technology are very effective in reducing radiation induced oxide damage, they are also more sensitive to Single Event Upset (SEU) effects due to their extremely reduced dimensions. This problem has to be addressed at the circuit level and generally leads to an area penalty. Several techniques have been proposed in literature with different trade-off between level of protection and cell size. A subset of these techniques has been implemented in the PANDA SPD ToPiX readout ASIC, ranging from DICE cells to triple redundancy. The two prototypes have been tested with several ions at the INFN-LNL facility in order to measure the SEU cross section. Comparative results of the SEU test will be shown, together with an analysis of the SEU tolerance of the various protection schemes and future plans for the SEU protection strategy which will be implemented in the next ToPiX prototype.
        Speaker: Giovanni Mazza (INFN sez. di Torino)
        Paper
      • 50
        Longevity of CMS ECAL Electronics
        The CMS Electromagnetic Calorimeter (ECAL) has played a vital role in the discovery of the Higgs Boson and other physics requiring the precise detection and measurement of electrons and photons. It is a homogenous lead tungstate scintillating crystal calorimeter with on-detector electronics based mainly on CMOS 0.25um ASICs and rad-hard gigabit optical links. The ECAL provides sums of energy of groups of up to 25 crystals, which are read-out at 40 MHz to be used as part of the level-1 trigger. On-detector circular buffers store the digital signals, with 12-bit precision, for up to 6.4us, sending the data out upon reception of a level-1 trigger. The ECAL will continue to be a critical component of CMS throughout the remainder of LHC operation, as well as during the precision study of, for example, Higgs physics at the High Luminosity LHC (HL-LHC) from about 2023 onwards. We assess the ability of the existing on-detector electronics to meet the demanding requirements of high luminosity running until 2035, including studies of the longevity of the electronics components and their susceptibility to ionizing and non-ionizing radiation. We conclude with an outline of possible upgrades to the electronics, both on-detector and off-detector.
        Speaker: Alessandro Bartoloni (Universita e INFN, Roma I (IT))
      • 51
        Radiation tolerance tests of SRAM-based FPGAs for the possible usage in the readout electronics for the LHCb experiment.
        This paper describes radiation studies of SRAM-based FPGAs as a central component of the electronics for a possible upgrade of the LHCb Outer Tracker readout electronics to a frequency of 40 MHz. Two Arria GX FPGAs were irradiated with 20 MeV protons to radiation doses of up to 7 Mrad. During and between the irradiation periods the different FPGA currents, the package temperature, the firmware error rate, the PLL stability, and the stability of a 32 channel TDC implemented on the FPGA were monitored. Results on the radiation tolerance of the FPGA and the measured firmware error rates will be presented. The Arria GX FPGA fulfils the radiation tolerance required for the LHCb upgrade (30 krad) and an expected firmware error rate of ~10^-6 Hz makes the chip viable for the LHCb Upgrade.
        Speaker: Christian Faerber (Ruprecht-Karls-Universitaet Heidelberg (DE))
        Paper
      • 52
        Acquisition and control command system for power pulsed detectors
        A DAQ system is developped within the SiW Ecal CALICE collaboration. It provides a flexible and scalable architecture, compound of three parts. A detector interface (DIF) extracting data from frontend electronics and sending them as packets. Two levels of data concentration, control clock and fast command fanout. The two cards, named DCC and GDCC, use respectively FastEthernet and GigaEthernet. A software suite (named Calicoes), for controlling DAQ, detector chips, acquiring data from GigaEthernet, decoding frontend readout to various formats and aggregating data. Overall architecture, performance in test beam and prospects for use with hundreds of thousands channels are discussed.
        Speaker: Frederic Bruno Magniette (Ecole Polytechnique (FR))
        Paper
      • 53
        DEPFET active pixel sensors for the vertex detector of the Belle-II experiment
        Active pixels sensors based on the DEPFET technology will be used for the innermost vertex detector of the future Belle-II experiment. The increased luminosity of the e+e- SuperKEKB collider entails challenging detector requirements, namely: low material budget, low power consumption, high precision and efficiency, and a huge readout rate. The DEPFET active pixel technology has shown to be the most suitable solution for this purpose. A review of the different aspects of the detector design (sensors, readout ASICS and supplementary infrastructure) and the results of the latest thinned sensor prototypes (50 μm) will be described.
        Speaker: Daniel Esperante Pereira (Universidad de Valencia (ES))
        Paper
        Poster
      • 54
        The management of large cabling campaigns during the Long Shutdown 1 of LHC.
        The consolidation and upgrade of the cabling infrastructure of the CERN accelerator complex is one of the most critical activities of the LHC Long Shutdown 1. This implies an extraordinary challenge in terms of project management, resource and activity planning, quality control and manpower organization. About 1000 km of both copper and optical fiber control cables have to be newly installed or replaced, representing an investment of about 15 MCHF. The preparation phase of this project started well before its implementation, by defining technical solutions and setting financial plans for staff recruitment and material supply. Enhanced task coordination was further implemented by deploying selected competences to form a central support team. A tool for progress monitoring was developed to facilitate the dynamic redistribution of manpower.
        Speaker: Stefano Meroli (Universita e INFN (IT))
        Paper
      • 55
        An Ultra-Fast Data Acquisition System for Coherent Synchrotron Radiation with YBCO Terahertz Detectors
        The recording of coherent synchrotron radiation requires DAQ systems with high temporal resolution. To resolve ultra-short terahertz pulses emitted by single bunch YBCO superconducting thin film detectors have been developed. A novel data acquisition system for sampling of the individual ultra-short terahertz pulses with high accuracy and real-time data processing is presented. The DAQ system is designed to sample the fast pulse signals with sampling times down to 3 ps. The data acquisition and the terahertz YBCO detectors have been tested at the synchrotron ANKA at KIT. The concept and the first results with single and multi-bunch filling pattern are discussed.
        Speaker: Michele Caselle (Karlsruhe Institute of Technology)
        Paper
        Poster
      • 56
        The sROD Module for the ATLAS Tile Calorimeter Phase-2 Upgrade Demonstrator
        TileCal is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider at CERN. The main upgrade of the LHC to increase the instantaneous luminosity is scheduled for 2022. The High Luminosity LHC, also called upgrade phase-2, will imply a complete redesign of the read-out electronics in TileCal. In the new read-out architecture, the front-end electronics aims to transmit full digitized information to the back-end system in the counting room. Thus, the back-end system will provide digital calibrated information with enhanced precision and granularity to the first level trigger to improve the trigger efficiencies. The demonstrator project has been envisaged to qualify this new proposed architecture. A reduced part of the detector, 1/256 of the total, will be upgraded with the new electronics during 2014 to evaluate the proposed architecture in real conditions.The sROD module is designed on a double mid-size AMC format and will operate under an AdvancedTCA framework. The module includes one Xilinx Kintex 7 and one Xilinx Virtex 7 for data receiving and processing, as well as the implementation of embedded systems. Related to optics, the sROD uses 4 Avago MiniPODs to receive data from the front-end electronics and 2 Avago MiniPODs to send control commands to the front-end and for communication with the first level trigger. A QSFP optical module is also included for expansion functionalities and a SFP module to maintain compatibility with the existing hardware.A complete description of the sROD module for the demonstrator including the main functionalities, circuit design and the control software and firmware will be presented.
        Speaker: Pablo Moreno (Universidad de Valencia)
        Paper
      • 57
        Front end strategy for the daq system of a Kinetic inductance detector
        Cosmology studies call for accurate measurements of cosmic microwave background radiation anisotropies. A promising technique to achieve the required precision is based on big arrays of Kinetic Inductance Detectors (KID). In this paper, we describe, a new strategy to stimulate and read a KID array of 128 pixels based on FPGAs and analog to digital converters. The project can reach an analog bandwidth as high as 250 MHz and all pixels can be stimulated and read continuously and in parallel. Results are sent to an on-line PC based farm via Ethernet or PCIexpress protocol.
        Speaker: Dedalo Marchetti (Universita' di Roma Tre)
      • 58
        The LHCb Muon Upgrade
        The LHCb collaboration is currently working on the upgrade of the experiment to allow, after 2018, an efficient data collection while running at an instantaneous luminosity of 2x1033/cm2s-1. The upgrade will allow 40 MHz detector readout, and events will be selected by means of a very flexible software-based trigger. The muon system will be upgraded in two phases. In the first phase, the off-detector readout electronics will be redesigned to allow complete event readout at 40 MHz. Also, part of the channel logical-ORs, used to reduce the total readout channel count, will be removed to reduce dead-time in critical regions. In a second phase, higher-granularity detectors will replace the ones installed in highly irradiated regions, to guarantee efficient muon system performances in the upgrade data taking conditions.
        Speaker: Alessandro Cardini (Universita e INFN (IT))
        Paper
      • 59
        Development of the readout system for Triple-GEM detectors for the CMS forward muon upgrade
        For the LHC high luminosity phases new triple-GEM detectors should be installed in the CMS muon endcap spectrometer, together with a new readout system. The functional requirements on the system are to provide both triggering and tracking information. In addition the system will be designed to take full advantage of current generic developments introduced for the LHC upgrades: CERN GLIB boards host in micro-TCA crates, the Versatile Link with the GBT chipset, etc. In this contribution the physics goals, the hardware architectures and expected performance of the CMS GEM readout system, including preliminary timing resolution simulations will be presented.
        Speaker: Thomas Lenzi (Universite Libre de Bruxelles (BE))
        Paper
      • 60
        A new approach to interfacing on-detector electronics
        The current off-chamber readout chain in the ATLAS experiment consists of sub-detector specific ReadOut Drivers (RODs), typically 9U VME cards, which receive data from a number of front-end links. The RODs build event fragments and forward these via point-to-point links, the Read-Out Links (ROLs) to the ReadOut System (ROS). The functionality of the RODs, not only consisting of fragment building but also of the associated error handling and for some subdetectors processing of the event data and also of support for calibration, is implemented in FPGAs and DSPs. For the Readout of new muon detectors to be installed during LS2 and for the Readout of all detectors after LS3 a new approach is foreseen, in which as much as possible functionality is moved to software. A similar system has been proposed for the LHCb experiment electronics upgrade in LS2. In this paper we present the new approach. We foresee that first results of tests can also be presented.
        Speaker: Lorne Levinson (Weizmann Institute of Science (IL))
        Poster
      • 61
        Development of Precision Time-Of-Flight Electronics for LHCb TORCH
        The TORCH detector is proposed for the low-momentum particle identification upgrade of the LHCb experiment. It combines Time-Of-Flight and Cherenkov techniques to achieve positive π/K/p separation up to 10GeV/c. This requires a timing resolution of 70ps for single photons. This paper will report on the electronics developed for such measurements, using commercial Micro Channel Plate devices and custom ASICs (NINO and HPTDC). The intrinsic timing resolution of the electronics measured with electrical test pulses is 40ps. With the photon detector and Cherenkov light, a resolution of 130ps has been recorded in a test beam.
        Speaker: Rui Gao (University of Oxford (GB))
        Paper
        Poster
      • 62
        Upgrade of the Muon Sorter in the Cathode Strip Chamber Level 1 Trigger System at CMS
        We report the results of our efforts in the past year to upgrade the Cathode Strip Chamber (CSC) Muon Sorter at CMS. After presenting an overview of the existing CSC Track Finder hardware and upgrade requirements we describe the modification of the existing board and transition to a new Muon Sorter. Then we discuss the improved sorting algorithm and its inplementation in firmware. Current status and future plans are outlined in the conclusion.
        Speaker: Mikhail Matveev (Rice University)
        Paper
        Slides
      • 63
        A Full Mesh ATCA-based General Purpose Data Processing Board
        High luminosity conditions at the LHC pose many unique challenges for potential silicon based track trigger systems. Among those challenges is data formatting, where hits from thousands of silicon modules must first be shared and organized into overlapping eta-phi trigger towers. Communication between nodes requires high bandwidth, low latency, and flexible real time data sharing, for which a full mesh backplane is a natural fit. A custom ATCA Data Formatter board is designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth board to board communication channels while keeping the design as simple as possible.
        Speaker: Jamieson Olsen (Fermilab)
        Paper
        Poster
      • 64
        Development of a digital trigger system to identify recoil protons at COMPASS-II
        The GANDALF framework has been developed to deliver a high precision, high performance detector readout and trigger system for particle-physics-experiments such as the COMPASS-II experiment at CERN. Combining the high performance pulse digitization and feature extraction capabilities of twelve GANDALF modules, each comprising a Virtex-5 SX95T, with the strong computation power of a Virtex-6 SX315T FGPA operated on the TIGER module, we present a digital trigger system for a recoil proton detector.
        Speaker: Matthias Gorzellik (Albert-Ludwigs-Universitaet Freiburg (DE))
      • 65
        NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs.
        The adoption of GPUs in the low level trigger systems is currently being investigated in several HEP experiments. While GPUs show a deterministic behaviour in performing computational tasks, data communication is the main source of fluctuations in the response time of such systems. We designed NaNet, a FPGA-based NIC supporting 1/10GbE links and the custom 34 Gbps APElink channel. The design has GPUDirect RDMA capabilities, i.e. is able to inject the input data stream directly into the Fermi/Kepler class GPU(s) memory, and features a network stack protocol offloading engine. We will provide a detailed description of the NaNet hardware modular architecture and a comparative performance analysis on the NA62 RICH detector GPU-based L0 trigger case study using the NaNet board and a commodity GbE NIC. Figures of merit for the system when using the APElink and 10GbE links will also be provided.
        Speaker: Alessandro Lonardo (Universita e INFN, Roma I (IT))
        Paper
        Slides
    • Plenary 3: Analog Design
      Convener: Christophe De La Taille (Inst. Nat. Phys. Nucl. & Particules (FR))
      • 66
        Continuous-Time Analog Filter Design in CMOS Nanoscale Era Town Hall, Congress Center

        Town Hall, Congress Center

        Perugia, IT

        <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
        The CMOS nanometer technologies represent a key opportunity for performance improvements, in terms of signal processing quality, power and area, but at the same time is an exciting challenge for analog designers to face MOS second-order effects present in scaled technologies which strongly modifies transistor behavior and operations. Innovative solutions will be presented to mitigate the problems of: - biasing Active-RC structures (critical for low VDD-VTH) - designing large bandwidth closed-loop (Active-RC) filter (critical for high-speed signals) - reducing the input referred noise (critical for achieving the same DR al lower VDD and, then, lower signal amplitude) - reducing the power consumption (critical for medium-linearity very high-speed applications)
        Speaker: Andrea Baschirotto (University of Milan-Bicocca)
        Paper
        Slides
    • Power, Grounding and Shielding: A3a
      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 67
        A new Rad-Hard DC/DC buck converter ASIC for LHC experiment upgrades
        In view of production for Phase1 LHC experiment upgrades a new DC/DC buck converter ASIC prototype has been designed and integrated in a commercial 0.35um technology. This circuit is called FEAST and it has been designed for radiation tolerance up to the tracker levels and it can operate in strong magnetic field. In particular resistance to Single Event Transient has been enhanced in comparison to previous prototypes. It provides stable voltage conversion from 12V to 600mV-5V with efficiency above 80%. It embeds also protection circuits as over-current, input under-voltage and over-current. FEAST design details, first functional and radiation tests will be presented.
        Speaker: Stefano Michelis (CERN)
        Slides
      • 68
        Power pulsing schemes for analog and digital electronics of the vertex detectors at CLIC
        The precision requirements of the vertex detector at CLIC impose strong limitations on the mass of such a detector (<0.2% of X0 per layer). To achieve such a low mass, ultra-thin hybrid pixel detectors are foreseen, while the mass for cooling and services will be reduced by implementing a power-pulsing scheme that takes advantage of the low duty cycle of the accelerator. The principal aim is to achieve significant power reduction without compromising the power integrity supplied to the front-end electronics. Voltage and current based power-pulsing schemes are proposed and their electrical features are discussed on the basis of measurements.
        Speaker: Cristian Alejandro Fuentes Rojas (CERN)
        Paper
        Slides
    • Trigger: B3a Trumpet 3, Congress Center

      Trumpet 3, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Wesley Smith (University of Wisconsin (US))
      • 69
        Hardware, firmware and software developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
        The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown.
        Speaker: Marco Ghibaudi (Scuola Superiore Sant'Anna di Studi Universitari e di Perfezion)
        Paper
        Slides
      • 70
        The Alice CTP upgrade
        After three years of successful operation of Alice Central Trigger Processor (CTP) system for proton-proton, Pb-Pb and p-Pb collisions, the Alice CTP is going to be upgraded with a new L0 board in order to improve the performance of the Alice trigger system. The new L0 board will include several new features: an additional trigger level "LM", which will precede the L0 trigger and will improve efficiency of data taking for the Transition Radiation Detector (TRD); a new 10G Ethernet link for CTP readout and control; an extension of the number of clusters and an extension of functionality for classes. Information for the classes with different BC masks will be registered in counters at each trigger level. In addition to these changes, which will come into effect in 2014 at the end of “Long Shutdown 1” (LS1), the first ideas for a CTP upgrade after “Long Shutdown 2” (LS2) in 2018 will also be presented.
        Speaker: Marian Krivda (University of Birmingham (GB))
        Slides
    • 10:40 AM
      Break
    • Radiation Tolerant Components and Systems: A3b
      Convener: Jorgen Christiansen (CERN)
      • 71
        Irradiation Tests and Expected Performance of Readout Electronics of the ATLAS Hadronic Endcap Calorimeter for the HL-LHC
        The readout electronics of the ATLAS Hadronic Endcap Calorimeter (HEC) will have to withstand an about 10 times larger radiation environment at the future high-luminosity LHC (HL-LHC) compared to the LHC design values. The radiation damages of the front-end electronics made in GaAs technology could significantly affect the HEC performance. Recent measurements of neutron and proton irradiation tests performed at LAr temperatures are reported, which allow an improved assessment of the expected degradation in HL-LHC conditions. These measurements are furthermore applied to simulations of the calorimeter performance. Results from replacement technologies, like Si CMOS, are also presented.
        Speaker: Faig Ahmadov (JINR)
        Paper
        Slides
      • 72
        Characterization of COTS ADC radiation properties for ATLAS LAr calorimeter readout upgrade
        The ATLAS LAr calorimeters plan to upgrade the readout electronics for both Phase-I and Phase-II LHC luminosity upgrades. Detector signals will be digitized at the front-end, and data will be streamed out to the back-end system continuously. Therefore, radiation tolerant ADCs are key components for both upgrade phases. This presentation will report on irradiation test results of commercial-off-the-shelf (COTS) ADCs that have potentials to be used in the readout electronics upgrade. Total-ionization-dose (TID) irradiation test results will be described, which has been used to pre-screen COTS ADCs for further studies. Various SEE studies of a candidate ADC with both neutron and proton beams will be presented. Finally, annealing studies following ATLAS policy on radiation tolerant electronics will be reported.
        Speaker: Helio Takai (Brookhaven National Laboratory (US))
        Slides
      • 73
        Performance of capacitively coupled active pixel sensors in 180 nm HV CMOS technology after irradiation to HL-LHC fluences
        We explore the concept of using a deep-submicron HV CMOS process to produce a drop-in replacement for traditional radiation-hard silicon sensors. Such active sensors contain simple circuits, e.g. amplifiers and discriminators, but still require a traditional (pixel or strip) readout chip. This approach yields most advantages of MAPS (improved resolution, reduced cost and material budget, etc.), without the complication of full integration on a single chip. After outlining the basic design of the HV2FEI4 test ASIC, results after irradiation with protons, x-rays and neutrons up to 1e16 neq/cm2 or 100MRad will be presented. Subsequently, design changes towards the optimised HV2FEI4_v2 are discussed and first irradiation results are shown before elaborating on future plans and general prospects of active sensors within ATLAS.
        Speaker: Simon Feigl (CERN)
        Paper
        Slides
    • Trigger: B3b Trumpet 3, Congress Center

      Trumpet 3, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Wesley Smith (University of Wisconsin (US))
      • 74
        Development and Testing of an Upgrade to the CMS Level-1 Calorimeter Trigger
        The LHC will restart in 2015 with a higher centre-of-mass energy and luminosity. To allow the CMS physics programme to fully exploit these increases the CMS Level-1 trigger must maintain similar efficiencies for searches and precision measurements to those achieved in 2012. With an average of 50 interactions occurring in each bunch-crossing, it will be challenging to select interesting physics events within the readout bandwidth limitations. The CMS calorimeter trigger is being upgraded to enable the more sophisticated algorithms needed to handle the high-luminosity conditions and to add the flexibility to adapt to changing LHC performance and physics priorities. The design of the upgraded system is summarised, performance of the prototype hardware presented, and the results of integration tests between subcomponents shown.
        Speaker: Dr Andrew William Rose (Imperial College Sci., Tech. & Med. (GB))
        Paper
        Slides
      • 75
        Real-time Topology Processing in the ATLAS Level-1 Calorimeter Trigger
        In 2015 the Large Hadron Collider will run with increased center-of-mass energy and luminosity. To maintain trigger efficiency against increased pileup rates, event topology information will be added to the ATLAS Level-1 real time data path and processed by a new Topology Processor (L1Topo). In phase-I, a new digital readout for the Liquid Argon calorimeters will provide finer granularity and depth segmentation in the electromagnetic layer to new Level-1 feature extractors (FEX) for improved EM, tau and jet identification. We present the topology and phase-I trigger upgrades to the ATLAS Level-1 trigger.
        Speaker: Pawel Piotr Plucinski (Stockholm University (SE))
        Paper
        Slides
      • 76
        The CMS MTF7 Trigger Board
        One of the workhorses for the CMS Level-1 Muon Trigger upgrade is the Muon Trackfinder board with a Virtex-7 generation FPGA (MTF7). Optimized to handle large input bandwidth for data from the different muon sub-detectors, the board also has 1 Gigabyte of fast access memory to be used as a look-up table while assigning muon momenta. We discuss the challenges and solutions for implementing the design with all these characteristics within the uTCA form factor, as well as projected performance, and results from test-stand runs with available prototypes.
        Speaker: Alexander Madorsky (University of Florida (US))
        Paper
        Slides
    • 12:25 PM
      Lunch
    • Plenary 4: Optoelectronics Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Francois Vasey (CERN)
      • 77
        What does it take to engineer and mass-produce a reliable parallel optics module… Or is it good enough to just have a good VCSEL and PIN array?
        Parallel optics modules are complex hybrid solutions that incorporate chip design of the VCSEL and PIN arrays plus optics design of the lens; a packaging design to provide thermal management and environmental protection; and an electrical subassembly that includes the IC and firmware. All of this needs to be designed to operate reliably over a long lifetime at worse case conditions. This is proven out thru extensive qualification testing. Designing and producing this complex product for high volume production also requires unique testing capabilities and process development. This presentation will highlight the design aspects involved in the development and manufacture of high speed parallel optics module.
        Speaker: Marco Fornasari (Avago Technologies)
    • Systems, Planning, Installation, Commissioning and Running Experience: A4 Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))
      • 78
        How to create successful open hardware projects - about White Rabbits and open fields
        CERN's accelerator control group has embraced "Open Hardware" (OH) to facilitate peer review, avoid vendor lock-in and make support tasks scalable. A web-based tool for easing collaborative work was set up and the CERN OH Licence was created. New ADC, TDC, Fine delay and carrier cards based on VITA and PCI-SIG standards were designed and drivers for Linux were written. Often industry was paid for developments, while quality and documentation was controlled by CERN. An innovative timing network was also developed with the OH paradigm. Industry now sells and supports these designs that find their way in new fields.
        Speaker: Erik Van Der Bij (CERN)
        Paper
        Slides
      • 79
        Integration Design Issues in HEP Experiments
        The global design process of high-energy physics experiments typically follows three overlapping stages consisting of detector modeling, detector integration and services implementation phases. This process sometimes results in unexpected interactions between subsystems. At the CMS experiment at CERN we have had over two years of operational experience during which time we have observed several instances of unexpected behavior attributable to the complexity of detector integration design. This presentation will examine the mechanisms and consequences of these behaviors, as well as considering their origins in the three level design process common to such experiments.
        Speaker: Sergei Lusin (University of Wisconsin (US))
        Slides
      • 80
        LogAmp electronics and optical transmission for the new SPS beam position measurement system.
        A new front-end electronics is under development for the SPS Multi Orbit POsition System (MOPOS). Based on logarithmic amplifiers, it allows to measure the beam position and to resolve the multi-batch structure of the SPS beams. Analogue data are digitized at 10 MS/s and packed in frames by an FPGA. On every turn, a frame is sent to the readout board, via a 2.4 Gb/s optical transmission link. The first prototype has been successfully tested with several SPS beams. The system description and the first measurement results are reported.
        Speaker: Caterina Deplano (CERN)
        Paper
        Slides
    • Trigger: B4 Trumpet 3, Congress Center

      Trumpet 3, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Emilio Petrolo (Istituto Nazionale di Fisica Nucleare Sezione di Roma 1)
      • 81
        Performance of the ALICE PHOS trigger and improvements for RUN 2
        This paper will discuss the performance of the PHOS level-0 trigger and planned improvements for RUN 2. Due to hardware constraints the Trigger Region Unit boards are limited to an operating frequency of 20 MHz. This has led to some ambiguity and biases of the trigger inputs. The trigger input generation scheme was therefore optimized to improve the performance. Proposed actions to further improve the performance and possibly eliminate the impact of the biased trigger inputs will also be presented. A level-1 trigger input is currently also being developed and tested.
        Speaker: Chengxin Zhao (University of Oslo (NO))
        Paper
        Slides
      • 82
        Design of a Hardware Track Finder (Fast Tracker) for the ATLAS Trigger
        The ATLAS Fast TracKer is a custom electronics system that will operate at the full Level-1 accept rate, 100 kHz, to provide high quality tracks as input to the Level-2 trigger. The event reconstruction is performed in hardware, thanks to the massive parallelism of associative memories (AM) and FPGAs. We present the advantages for the physics goals of the ATLAS experiment and the recent results on the design, technological advancements and testing of some of the core components used in the processor.
        Speaker: Guido Volpi (Istituto Nazionale Fisica Nucleare (IT))
        Paper
        Slides
      • 83
        The FPGA based Trigger and Data Acquisition system for the CERN NA62 experiment
        The main goal of the NA62 experiment at CERN is to measure the branching ratio of the ultra-rare K+ → π+νν decay, collecting about 100 events to test the Standard Model of Particle Physics. Readout uniformity of sub-detectors, scalability, efficient online selection and lossless high rate readout are key issues. The TDCB and TEL62 boards are the common blocks of the NA62 TDAQ system. TDCBs measure hit times from sub-detectors, TEL62s process and store them in a buffer, extracting only those requested by the trigger system. During the NA62 Technical Run at the end of 2012 the TALK board has been used as prototype version of the L0 Trigger Processor.
        Speaker: Bruno Angelucci (Sezione di Pisa (IT))
        Paper
        Slides
    • 4:05 PM
      Break
    • Poster: Second part
      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 84
        SALT - new silicon strip readout chip for the LHCb Upgrade
        The LHCb detector, operating at the LHC proton-proton collider, has finished its Run I period. After more than two years of collision data taking the experiment accumulated corresponding integrated luminosity of around 3.1 fb-1. The full recorded data sample will be used by physicsts to search for New Physics and precise measurement of CP-violation in heavy flavor quark sector. Despite its superb performance it is clear that the LHCb experiment is statistically limited for a number of important decay channels (such as Bd->K*mumu or Bs->phiphi). This, in turn, is related to the current data acquisition architecture which can acquire data at the top rate of 1.1 MHz at the instantaneous luminosity close to 4x10^32 [cm-2s-1]. The LHC machine is already capable of delivering more than one order of magnitude higher luminosity that is presently used by the LHCb. This fact led the LHCb Collaboration to preparing a proposal regarding an upgrade of the LHCb spectrometer that would allow it to exploit higher luminosities (up to 2x10^33), greatly improve the trigger efficiencies for both hadronic and leptonic decay modes. The upgrade will allow the experiment to collect about 50 fb-1 of data. One of the most important topic of the LHCb upgrade is design and implementation of new front-end electronics allowing a full detector read-out at the bunch-crossing rate of 40 MHz. This will be further augmented by a software trigger that will be capable of processing the data at the same rate. This talk presents a novel design of the common readout chip for silicon strip detectors which will be able to digitise the analogue signal on-detector and subsequently perform digital processing and zero-suppression.
        Speaker: Krzysztof Piotr Swientek (AGH University of Science and Technology (PL))
      • 85
        Digital Column Readout Architectures for Hybrid Pixel Detector Readout Chips
        In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256x256 pixels with a pixel pitch of 55um. The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured data are compared. The second architecture has been designed for Velopix, a readout chip planned for the LHCb upgrade. Unlike Timepix3, this has to be tolerant to radiation-induced single-event effects. Results from post-layout simulations are shown with the detailed circuit architectures.
        Speaker: Tuomas Sakari Poikela (University of Turku (FI))
        Paper
      • 86
        The eCDR, a Radiation-Hard 40/80/160/320 Mbit/s CDR with internal VCO frequency calibration and 195 ps programmable phase resolution in 130 nm CMOS
        A clock and data recovery IP, the eCDR, is presented which is intended to be implemented on the detector front-end ASICs that need to communicate with the GBTX by means of e-links. The programmable CDR accepts data at 40, 80, 160 or 320 Mbit/s and generates retimed data as well as 40, 80, 160 and 320 MHz clocks that are aligned to the retimed data. Moreover, all the outputs have a programmable phase with a resolution of 195 ps. The radiation-hard design, integrated in a 130 nm CMOS technology, operates at a supply voltage between 1.2 V and 1.5 V.
        Speaker: Filip Francis Tavernier (CERN)
        Paper
      • 87
        Characterization results and first applications of KLauS - an ASIC for SiPM charge and fast discrimination readout
        KLauS is an ASIC produced in the AMS 350nm SiGe process to read out the charge signals from silicon photomultipliers. Developed as an analog frontend for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with a high precision. In order to compensate bias and temperature fluctuations of each sensor individually, an 8-bit DAC to tune the voltage at the input terminal within a range of 2V is implemented. Using an integrated fast comparator with low jitter, the time information can be measured with sub-nanosecond resolution. The low power consumption of the ASIC can be further decreased using power gating techniques. Future versions of KLauS are under development and will incorporate an ADC with a resolution of up to 12 bit and blocks for digital data transmission. Most recent characterization results for the KLauS chip are presented as well as results from a KLauS-based test setup developed for mass characterisation of scintillator tiles used in the AHCAL test beam program.
        Speaker: Tobias Harion (Kirchhoff-Institut Heidelberg)
        Paper
      • 88
        FEERIC, a very-front-end ASIC for the ALICE Muon Trigger Resistive Plate Chambers
        The ALICE Collaboration at the CERN-LHC has started a vast program of upgrades of the detector in the context of the increase of the luminosity of the LHC from 2018 on. The present very front-end electronics (VFE) of the Muon Trigger, whose acronym is ADULT, must be replaced to limit the aging of the Resistive Plate Chambers (RPCs) in the future expected operating conditions. For this purpose, the new VFE, FEERIC, will have to perform an amplification of the analog input signal (this is not the case for ADULT). This will allow to operate the RPCs in avalanche mode with a lower gain at the level detectorgas, in comparison to the current situation. This VFE represents 21,000 channels, distributed over 2400 electronics cards equipped with one or two FEERIC ASICs. A total of 3000 ASICs of 8 channels each is necessary. The future ASIC has to insure mainly the following functions: amplification, discrimination and LVDS output stage. FEERIC will be capable of handling bipolar signals varying from ±20 fC up to ±5 pC. A prototype chip has been designed using the 0.35 μm CMOS technology of AMS. The FEERIC ASIC description, technical choices and performance from simulations and tests will be presented.
        Speaker: Samuel Pierre Manen (Univ. Blaise Pascal Clermont-Fe. II (FR))
      • 89
        Prototype pixel detector in the SOI technology
        We present the prototype pixel detector built in the Silicon on Insulator (SOI) technology. The sensor matrix contains 1024 integrating type cells, read continuously out as a serial analog signal. The pixels are protected from the back-gate effect by the Buried P-Well implantations. Measured ENC value was found to be 130 electrons at 100us integration time. An on-chip prototype SAR ADC and a precise voltage reference and temperature sensors have been also included in the design
        Speaker: Piotr Kapusta (Institute of Nuclear Physics PAN, Krakow (PL))
        Paper
      • 90
        Development of New Front-end Electronics for the Upgrade of the ATLAS Muon Drift Tube Chambers at High LHC Luminosity
        New ATLAS Monitored Drift Tube (MDT) chambers with reduced tube diameter (sMDT) - 15 mm instead of 30 mm - have been developed for LHC luminosity upgrades. The shorter lengths of the pulse trains due to the smaller tube diameter allow to operate the sMDTs at much higher rates, however the gain in efficiency is limited by the shaping scheme of the current ASD (Amplifier-Shaper-Discriminator) chip. We present measurements and simulations with alternative shaping using active baseline restoration (BLR), evaluate the possible improvement in efficiency, and report on the design of a new front-end chip implementing this feature (BLR).
        Speaker: Philipp Schwegler (Max-Planck-Institut fuer Physik (Werner-Heisenberg-Institut) (D)
      • 91
        VIPRAM – 2D Prototype and 3D Design
        Associative memory based track finding has been proven to provide a unique solution to fast silicon-based track trigger in the hadron collider environment. Future LHC experiments will demand greater speed and more patterns. While it is unlikely that scaling of 2D technology will satisfy the needs in a cost effective way, 3D Vertical Integration offers the possibility of dramatic improvements. The Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) concept has been presented before. In this talk, we present details of the 2D prototype design, test results of fabricated chips with comparison to simulation studies and future project directions.
        Speaker: Jim Hoff (Fermilab)
      • 92
        Design and characterization of a GAPD pixel detector prototype for future particle trackers
        A monolithical GAPD (Geiger-mode Avalanche PhotoDiode) detector aimed to particle tracking at future linear colliders is being developed. A first prototype of a bidimensional GAPD pixel array has been designed and fabricated with a conventional 0.35 µm HV-CMOS process. The experimental characterization of the device shows that the expected noise counts generated by the sensor can be reduced to ~10E-7 fake pulses per bunch by time-gating the detector in the nanosecond scale while reducing the working temperature to -20 ºC. The design and complete characterization of the GAPD detector will be presented at the conference.
        Speaker: Eva Vilella-Figueras (Universitat de Barcelona)
      • 93
        TRB3 264 Channel High Precision TDC Platform and Its Applications
        The TRB3 features four FPGA-based TDCs with <20ps RMS time precision between two channels and 256+4+4 channels in total. One central FPGA provides flexible trigger functionality and GbE connectivity including powerful slow control. We present recent users' applications of this platform following the COME&KISS principle: Successful test beamtimes at CERN (CBM), in Juelich and Mainz with an FPGA-based discriminator board (PaDiWa), a charge-to-width FEE board with high dynamic range, read-out of the n-XYTER ASIC and software for data unpacking and TDC calibration in ROOT. We conclude with an outlook on future developments.
        Speaker: Andreas Neiser (Institute of Nuclear Physics, Mainz - Germany)
        Paper
        Poster
      • 94
        Design of a deterministic link initialization mechanism for serial LVDS interconnects
        The Compressed Baryonic Matter experiment at FAIR in Darmstadt has special requirements on the Data Acquisition Network. One of them is deterministic latency of all links from the back-end to the front-end, which enables synchronization in the whole read-out tree. Since front-end electronics (FEE) contains mixed-signal circuits for processing of detector raw data, special ASICs were developed. DDR LVDS links are used as interconnects between FEEs and readout controllers. An adapted link initialization mechanism ensures determinism for them by balancing cable lengths, adjusting phase differences and handling of environmental behavior. After re-initialization timing precision has to be on bit-clock level.
        Speaker: Sven Schatral (University of Heidelberg)
        Paper
        Slides
      • 96
        Evaluation of 400m, 5Gbit Versatile Link lengths over OM3 and OM4 fibres for the LHCb upgrade
        The LHCb experiment will upgrade its DAQ system to a trigger less, 40MHz read-out after LS2. To be able to process the approximately 40Tbit/s of data we will require a massive computing farm. This computing farm can not be installed underground, in the vicinity of the detector anymore due to the enormous power and cooling requirements. An affordable data transport solution has to be found to carry the data from the detector to the new data center on the surface. The distance to cover is estimated to be between 300 and 400 meters. We evaluated the feasibility of using the 5Gbit/s Versatile Link to cover the full distance over OM3 and OM4 quality fibres and will present our results.
        Speaker: Rainer Schwemmer (CERN)
        Paper
      • 97
        The 120Gbps VCSEL array based optical transmitter (ATx) development for the High-Luminosity LHC (HL-LHC) experiments
        The integration of VCSEL array and driving ASICs in a custom optical transmitter module (ATx) for operation in the detector front-end is demonstrated. The ATx provides 12 parallel channels with each channel operating at 10 Gbps. The assembly comprises a ceramic substrate with high-density wiring for electrical interface, OE components, and a micro-lens array with guiding structure for optical interface. Commercial driver is currently used on the demonstrator and will be replaced by a radiation tolerant driver. The complete module with ASIC shielded is to be irradiated under x-ray with total dose over 10Mrad.
        Speaker: Jingbo Ye (Southern Methodist University (US))
        Paper
        Slides
      • 98
        Versatile Transceiver and Transmitter Production Status
        Production of the Versatile transceiver and twin transmitter modules for use in the readout and control systems of upgrading LHC detector systems is starting. We review the performance of the prototypes produced so far and show that the modules are ready for production. We outline the commercial actions being taken to procure parts and assemblies and show the production plan for delivering known good parts in the various flavours required for the upgrade projects that will be using them.
        Speaker: Jan Troska (CERN)
        Paper
      • 100
        The high voltage power supplies of the CREAM experiement
        Abstract : The environment conditions of the Long Duration Balloon flight are the worst possible for high voltage electronics which must survive at the altitude of 40km and a pressure of 5mbar in the Payload of the CREAM (COSMIC Ray Energy And Mass) balloon. Three different high voltage power supplies (1400V, 2000V and 12000V with a maximum consumption of 20 mA per module) were developed at LPSC for 3 CREAM sub-detectors. The power supplies developed were based on two specific constraints. First, the sensitive cosmic ray detectors need very low noise and stable power (mettre un exemple si il te reste des mots). Secondly, the operation near the minimum of the Paschen curve lower the breakdown voltage to 300V/mm compared to 1KV/mm at sea level.
        Speaker: Ludovic Eraud (LPSC,Centre National de la Recherche Scientifique (FR))
        Slides
      • 101
        Pulsed power distribution for power supply isolation and remote 2-wire point-of-load regulation for the ATLAS Pixel Detector
        High common mode offset voltages can arise in the ATLAS Pixel detector module communication links that could prevent new Pixel Detector modules from taking data because of the present grounding and power supply schemes. Isolation of all the detector module electronics supply channels eliminates this risk. We propose that it is possible to provide inexpensive, reliable and serviceable power channel isolation by exploiting the ac characteristics of the installed ATLAS Pixel power distribution system. We also show how it is possible to achieve remote, 2-wire point-of-load voltage regulation by using pulsed power over existing Pixel cables.
        Speaker: A A Hasib (University of Oklahoma (US))
        Paper
      • 102
        The new NA62 LKr readout: first tests and future perspectives
        The NA62 experiment at the CERN SPS (Super Proton Synchrotron) accelerator aims at studying ultra-rare kaon decays. The high resolution Liquid Krypton (LKr) calorimeter, built for the NA48 experiment, is a crucial part of the NA62 photon-veto system. However, the back-end electronics of the LKr calorimeter has to be redone in order to accommodate the new requirements. The exhaustive specification was prepared and the decision to sub-contract the development and production of the acquisition board to industry was taken in 2011. This paper presents the primary test results of the Calorimeter REAdout Module (CREAM) prototype delivered by the manufacture in March 2013. All essential features, analog performance, trigger properties, data processing and readout, are covered.
        Speaker: Stefano Venditti (Sezione di Pisa (IT))
        Paper
      • 103
        System Level and Production Tests of the CMS HCAL QIE10
        The CMS Hadron Calorimeter (HCAL) is scheduled to be upgraded to increase longitudinal depth segmentation in the Barrel and Endcap regions and to improve anomalous signal rejection efficiency in the Forward Region.  In order to achieve these goals, the phototransducers and the front-end and back-end electronics of the HCAL will be upgraded in stages over the next several years.   New PMTs in the Forward Detector and silicon photomultipliers (SiPMs) in the Barrel and Endcap detectors will be read out with charge integrator and encoder (QIE) deadtimeless Flash ADCs operating at 40 MHz.  During the HCAL Upgrade, the current QIE Version 8 (QIE8) chip will be replaced by the next generation QIE10 chip, which features a ten times greater dynamic range and the inclusion of TDC data with 0.5 ns resolution.  The HCAL back-end electronics will be upgraded from a VME readout system to a micro-TCA achitecture.  We present the results of system integration tests of the QIE10 chip's operation within the full front-end to back-end electronics chain.  We also present the current progress of production chip testing of the QIE10, which involves the robotic ASIC tester at Fermilab.
        Speaker: Gary Drake (Argonne National Laboratory (US))
      • 104
        Consolidation of the radiation tolerant programmable power supply cards for the LHC beam screen heaters
        For the next LHC run it is required to install 200 W of heating capacity to regenerate the beam screen by desorption of gas trapped on its walls. In the LHC, there are 272 beam screen heaters and the associated electronics limits the heating capacity to 25 W. These electronics are mostly installed inside the LHC tunnel and exposed to its radiation environment. This paper describes the basic functionalities of the new card and the work done for designing and qualifying under radiation an analog signal multiplexer and a power switch capable of coping with the grid voltage.
        Speaker: Nikolaos Trikoupis (CERN)
        Paper
        Poster
      • 105
        Single event upsets in the readout control FPGA of the ALICE TPC detector during the first LHC running period
        This paper will present and discuss measurement results of single event upsets in the readout control FPGA of the ALICE Time Projection Chamber during the first LHC running period. The measurements have been performed during stable beam conditions for proton-proton, proton-lead and lead-lead collisions.
        Speaker: Johan Alme (Department of Physics and Technology)
      • 106
        10 Order of OF Magnitude Current Measurement Digitizers for the CERN Beam Loss Systems.
        A wide range current digitizer card is needed for the acquisition module of the beam loss monitoring systems in the CERN Injector Complex. The fully differential frequency converter allows measuring positive and negative input currents with a resolution of 31nA in an integration window of 2µs. Increasing the integration window, the dynamic range covers 2•1010 were the upper part of the range is converted by measuring directly the voltage drop on a resistor. The key elements of this design are the fully differential integrator and the switches operated by an FPGA. The circuit is designed to avoid any dead time in the acquisition and reliability and failsafe operational considerations are main design goals. The circuit will be discussed in detail and lab and field measurements will be shown
        Speaker: William Vigano (CERN)
        Paper
      • 107
        ATLAS Diamond Beam Monitor
        The Diamond Beam Monitor (DBM) is a pCVD diamond pixel tracker for detecting high-energy charged particles. It is planned to be installed in the ATLAS experiment at CERN for the luminosity measurements. In this talk, the overview of the DBM system and the operation of the diamond pixel sensors are described.
        Speaker: Matevz Cerv (CERN)
        Paper
      • 108
        Mitigation of Radiation and EMI effects on the Vacuum Control System of LHC
        The 26 km of vacuum chambers where circulates the beam of LHC (Large Hadron Collider) must be maintained under UHV (Ultra High Vacuum) to minimize the beam interaction with residual gases, and allow the operation of specific systems. The vacuum is measured by several thousands of gauges along the accelerator. Bad vacuum measurements may trigger a beam dump and close the associated sector valves. The effects of radiation or EMI (Electromagnetic Interferences) on components that may stop the machine must be evaluated and minimized. We report on the actions implemented to mitigate their impact on the vacuum control system.
        Speaker: Gregory Pigny (CERN)
      • 109
        Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
        The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.
        Speaker: Fernando Carrio Argos (Universidad de Valencia (ES))
        Paper
      • 110
        The AMC13XG: A New Generation Clock/Timing/DAQ Module for CMS MicroTCA
        The AMC13 provides clock, timing and DAQ service for many subdetectors and central systems in the upgraded CMS detector. This year we have developed an upgraded module, the AMC13XG, which supports 10 gigabit optical fiber and backplane interfaces. Many of these modules are now being installed in the CMS experiment during the current LHC shutdown. We describe the implementation using Xilinx Kintex-7 FPGAs, commissioning, production testing and integration in the CMS HCAL and other subsystems.
        Speaker: Eric Shearer Hazen (Boston University (US))
        Paper
      • 111
        Simulation of ATLAS SCT module response to LHC beam loss scenarios
        In the event of beam loss at the LHC, ATLAS inner detector components nearest the beamline may be subjected to unusually large amounts of radiation. Understanding their behavior in such an event is important in determining whether they would still function properly. We built a SPICE model of the silicon strip module electrical system to determine the behavior of its elements during a realistic beam loss scenario, and to decide which further tests of the silicon strip detector system are necessary. We found that the power supply and bias filter characteristics strongly affect the module response in such scenarios.
        Speaker: Peyton Rose (University of California,Santa Cruz (US))
        Paper
      • 112
        The readout electronic of EUSO-Balloon experiment
        A complex readout electronic chain has been designed for the EUSO-Balloon project. It contains two elements: the EC units (9 of them) and the EC-ASIC boards (6). The EC unit includes 64-channel Multi-Anode Photomultipliers and a set of pcbs used to supply the 14 different high voltages needed by the MAPMTs and to read out the analog output signals. These signals are transmitted to the EC-ASIC boards which contain 6 SPACIROC ASICs each. During the year 2012, prototypes of each board were produced and tested successfully, leading to the production of the flight model pcbs.
        Speaker: Thierry Caceres (LAL Orsay)
        Paper
      • 113
        Performance evaluation of multiple (16 channels) sub-nanosecond TDC implemented in low-cost FPGA
        NA62 experiment Straw tracker frontend board serves as a gas-tight detector cover and integrates two CARIOCA chips, a low cost FPGA (Cyclon III, Altera) and a set of 400Mbit/s links to the backend. The FPGA houses 16 sub-nanosecond resolution TDCs with derandomizers and an output link serializer. Evaluation methods, including simulations, and performance results of the system in the lab and on a detector prototype are presented.
        Speaker: Georgios Konstantinou (National Technical Univ. of Athens (GR))
        Paper
      • 114
        The upgrade of the LHCb calorimeter
        The LHCb collaboration foresees a major upgrade of the detector for the high luminosity run that should take place after 2018. Apart from the increase of the instantaneous luminosity at the interaction point of the experiment, one of the major ingredients of this upgrade is a full readout at 40MHz of the sub-detectors and the acquisition of the data by a large farm of PC. The trigger will be done by this farm and should increase the overall trigger efficiency with respect to the current detector, especially in hadronic B meson decays. A general overview of the modifications foreseen to the calorimeter system and the integration of the electromagnetic and hadronic calorimeters in this new scheme will be described.
        Speaker: Juan Mauricio Ferre (University of Barcelona (ES))
      • 115
        Common control and readout board for the Calorimeter and Tracker Front-end electronics of the SuperNEMO experiment.
        SN_CROB board is the common Control and Readout Board for the Calorimeter and Tracker Front-end electronics of the SuperNEMO experiment. SuperNEMO is the next-generation (0) experiment based on a tracking plus calorimetry technique. The demonstrator is made of a calorimeter (700 channels) and a tracking detector (6000 channels). These detectors front-end electronics use an unified architecture based on similar crates. SN_CROB board gathers the front-end data from the calorimeter or tracker FEBs and sends them through Ethernet link to the DAQ. It extracts the Trigger Primitive from the front-end data and sends them through serial link to the Trigger Board.
        Speaker: Thierry Caceres
      • 116
        Simulation of the ATLAS sTGC trigger for the Phase-I new small wheel detector upgrade
        A Verilog Behavioral simulation of sTGC trigger will be presented based on the current baseline concept with particular focus on the Level 1 latency obtained. Data for this trigger is taken from detector simulations with Garfield and PSpice, current measurements made in the existing small wheel, and FLUGG simulation of the arrival times of hits at high luminosities. These simulations will become the HDL that is used to compile the ASIC in the 130nm IBM CMOS process. The CERN designed GBT serializer is to be included in the ASIC for transmission of the resulting trigger information to the rim of the nSW.
        Speaker: Jay Chapman (University of Michigan, Ann Arbor, Michigan, 48109, USA)
      • 117
        The CMS Global Muon Trigger upgrade
        To continue triggering with the current performance in the LHC Run 2 the Global Muon Trigger (GMT) of the CMS experiment will be reimplemented in a Virtex-7 card utilizing the uTCA architecture. The thus available high-capacity input as well as increased logic could be used to migrate the final sorting stage of each subsystem to the GMT. Additionally the GMT will calculate a muon’s isolation using energy information received from the calorimeter trigger which will be propagated to the Global Trigger. A summary of the current status of the future GMT’s development will be given.
        Speaker: Dinyar Rabady (University of Vienna (AT))
        Paper
    • 7:30 PM
      Visit of the museum of wine and oil in Torgiano Torgiano, IT

      Torgiano, IT

    • 8:30 PM
      Conference Dinner Torgiano, IT

      Torgiano, IT

    • Plenary 5
      Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))
      • 118
        Chips developed at CERN in the framework of the Medipix3 Collaboration
        This contribution will review on-going ASIC developments taking place within the context of the Medipix3 Collaboration and also discuss a development aimed at a future CLIC vertex detector. We will begin with a description of the Medipix3RX ASIC and its innovative architecture. The measurement results and the lessons learned in the project will be covered in detail. We will discuss the novel aspects of the on-going and future developments (the Dosepix, Timepix3, Smallpix, and CLICpix prototype ASIC). This will also include discussion on hybrid pixel detector readout chip compatibility with Through Silicon Via technology (TSVs) and the exploration of more downscaled technologies.
        Speaker: Rafael Ballabriga Sune (CERN)
        Slides
    • ASICs: B5a Trumpet 3, Congress Center

      Trumpet 3, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Luciano Musa (CERN)
      • 119
        Characterization of the CBC2 readout ASIC for the CMS strip-tracker high-luminosity upgrade
        The CMS Binary Chip 2 (CBC2) is a full-scale prototype ASIC developed for the front-end readout of the high-luminosity upgrade of the CMS silicon strip Tracker. The 254-channel, 130nm CMOS ASIC is designed for the binary readout of double-layer modules, and features cluster-width discrimination and coincidence logic for detecting high-PT track candidates. The chip was manufactured in January 2013 and has since been bump-bonded to a dual-chip hybrid and extensively tested. The CBC2 is fully functional and working to specification: we present the result of electrical characterization of the chip, including gain, noise, threshold scan and power consumption, together with the performance of the stub finding logic. Finally we will outline the plan for future developments towards the production version.
        Speaker: Davide Braga (STFC - Science & Technology Facilities Council (GB))
        Paper
        Slides
      • 120
        Development of Dedicated Front--end Electronics for Straw Tube Tracker in PANDA Experiment
        The design and measurements of front--end electronics for straw tubes tracker (STT) at PANDA experiment are presented. The challenges for front--end electronics are discussed and the proposed architecture comprising switched gain preamplifier, pole--zero cancellation circuit (PZC), variable peaking time shaper, ion tail cancellation circuit (TC) and baseline holder (BLH) is described. The front--end provides analogue amplitude output and leading edge discriminator (LED) output for time and time--over--threshold (ToT) measurements. The first prototype ASIC comprise four channels was fabricated in 0.35~$\mu $m CMOS technology. The results of measurements on ion tail cancellation, gain, noise, time walk and jitter are presented.
        Speaker: Dominik Wladyslaw Przyborowski (AGH University of Science and Technology (PL))
        Slides
    • Optoelectronics and Links: A5a
      Convener: Francois Vasey (CERN)
      • 121
        A 65-nm-CMOS-process-based 10-Gbps VCSEL driver
        A VCSEL driver has been designed and fabricated in a SMIC 65-nm CMOS process. The preliminary testing results show the ASIC can work at 10 Gbps without peaking or emphasis structures. Due to the thin gate oxide of the technology and large size transistors used in the design, the VCSEL driver is potential radiation tolerant. We will present the irradiation testing results in the conference. To the best of our knowledge, the ASIC is the first VCSEL driver designed in a 65-nm CMOS process for high energy particle physics experiments.
        Speaker: Jingbo Ye (Southern Methodist University, Department of Physics)
        Paper
        Slides
      • 122
        An optical data transmission ASIC for the ATLAS liquid argon calorimeter upgrade
        We present several ASICs of optical data transmission for the ATLAS liquid argon calorimeter trigger upgrade. These ASICs include a two-channel serializer (LOCs2), a single-channel and a four-channel VCSEL driver (LOCld1 and LOCld4), each channel operating at 8 Gbps. The serializer ASIC implements a low-latency, low-overhead, quick-resynchronization interface chip (LOCic) between ADCs and serializers. These ASICs are designed and fabricated in a commercial 0.25-μm silicon-on-sapphire (SoS) CMOS technology, which is suitable for high energy physics front-end electronics applications. The designs and test results will be presented.
        Speaker: Xiaoting Li (Central China Normal University, Southern Methodist University)
        Paper
        Slides
    • 10:40 AM
      Break
    • ASICs: B5b Trumpet 3, Congress Center

      Trumpet 3, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Luciano Musa (CERN)
      • 123
        SPADIC - Self-triggered charge pulse processing ASIC for CBM-TRD
        For the readout of the transition radiation detectors of the upcoming CBM experiment at FAIR, a self-triggered multi-channel mixed signal ASIC for signal amplification, digitization, and processing is under development. The SPADIC 1.0 chip has 32 channels, each composed of a charge sensitive amplifier, a 9 bit pipelined ADC continuously running at 25 MHz sampling rate and a programmable digital filter for detector specific tasks such as tail cancellation and baseline correction. The readout of whole signal snapshots is triggered by hit detection logic in each channel, or by selected neighbor channels. Data messages from the channels are multiplexed to a single output data stream preserving the order in which the hits were recorded. The proper function of the ASIC has already been demonstrated in the lab and at a CERN beamtime. Further characterization is going on.
        Speaker: Michael Krieger (University of Heidelberg)
        Slides
      • 124
        Design and Performance of the VMM1 ASIC for Micropattern Gas Detectors
        Measurements of the first prototype VMM1 ASIC designed at Brookhaven National Laboratory in 130 nm CMOS and fabricated in spring 2012 are presented. The 64-channel ASIC features a novel design for use with several types of micropattern gas detectors. The data driven system measures peak amplitude and timing information in tracking mode including sub-threshold neighbors and first channel hit address in trigger mode. Several programmable gain and integration times allows the flexibility to work with Micromegas, Thin Gap Chambers (TGCs), and Gas Electron Multiplier (GEM) detectors. The IC design and features are presented along with measurements characterizing the performance of the VMM1 such as noise, linearity of the response, time walk, as well as calibration and performance measurements taken with a Micromegas detector.
        Speaker: Jessica Metcalfe (Brookhaven National Laboratory (US))
        Slides
      • 125
        QIE10: A New Front-End Custom Integrated Circuit
        We present results on a new version of the QIE (Charge Integrating Encoder), a custom Application Specific Integrated Circuit (ASIC) designed at Fermilab. Developed specifically for the measurement of charge from detectors in high-rate environments, this most recent addition to the QIE family features 3 fC sensitivity, 17-bits of dynamic range with logarithmic response, a Time-to-Digital Converter (TDC) with sub-nanosecond resolution, and internal charge injection. The device is capable of dead-timeless operation at 40 MHz, making it ideal for calorimetry at the Large hadron Collider (LHC). We present bench measurements and integration studies that characterize the performance, radiation tolerance measurements, and plans for deployment in the Atlas and CMS detectors as part of the Phase 1 and Phase 2 upgrades.
        Speaker: Gary Drake (Argonne National Laboratory)
        Paper
        Slides
    • Optoelectronics and Links: A5b Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Francois Vasey (CERN)
      • 126
        Single Event Upset Studies Using the ATLAS SCT
        Single Event Upsets (SEU) are expected to occur during high luminosity running of the ATLAS SemiConductor Tracker (SCT). The SEU cross sections were measured in pion beams with momenta in the range 200 to 465 MeV/c and proton test beams at 24 GeV/c but the extrapolation to LHC conditions is non-trivial because of the range of particle types and momenta. The SEUs studied occur in the p-i-n photodiode and the registers in the ABCD chip. Comparisons between predicted SEU rates and those measured from ATLAS data are presented. The implications for ATLAS operation are discussed.
        Speaker: Anthony Weidberg (University of Oxford (GB))
        Paper
        Slides
      • 127
        Gamma Irradiation of Minimal Latency Hollow-Core Photonic Bandgap Fibres
        Hollow-core photonic-bandgap fibres (HC-PBGFs) offer many advantages over conventional fibres, such as low latency and radiation hardness; properties that make HC-PBGFs interesting for the HEP community. This contribution presents the results of gamma irradiation tests carried out using a new type of HC-PBGFs that combines low enough attenuation over distances that are reasonable for HEP applications together with a transmission bandwidth that covers the 1550nm region. The HC-PBGF showed two orders of magnitude lower radiation induced attenuation than a conventional single-mode fibre during a 67.5h exposure to gamma-rays, resulting in an RIA of 2dB/km at an accumulated dose of 1MGy.
        Speaker: Lauri Juhani Olantera (CERN)
        Paper
        Slides
      • 128
        System-level Testing of the Versatile Link Components
        During the first upgrade phase of the Large Hadron Collider experiments, high-speed optical links will be deployed to achieve the bandwidth needed to exploit the increasing luminosity and to allow data acquisition at higher rates. The Versatile Transceiver (VTRx) and Versatile Twin Transmitter (VTTx) modules are in their final development phase before production. They support different link architectures and offer compatibility with either single-mode or multi-mode fibre plants. This paper describes the supported link configurations and presents the system-level testing of the VTRx and VTTx front-end modules with various commercial-off-the-shelf back-end components.
        Speaker: Csaba Soos (CERN)
        Paper
        Slides
    • 12:25 PM
      Lunch
    • Plenary 6
      Convener: Livio Mapelli (CERN)
      • 129
        Biologically-Inspired Massively-Parallel Computation
        The SpiNNaker (Spiking Neural Network Architecture) project aims to deliver a machine, ultimately incorporating a million ARM processors, optimised for running large-scale models of systems of spiking neurons running in biological real time. The major challenge in developing the machine has been to reproduce the very high levels of connectivity found in the brain; this has been achieved by using a very lightweight multicast packet-switched network that can carry very large numbers of very small packets, each carrying information about an individual neural spike.
        Speaker: Steve Furber
        Slides
    • ASICs: B6 Trumpet 3, Congress Center

      Trumpet 3, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Marcus Julian French (STFC - Science & Technology Facilities Council (GB))
      • 130
        PETA4 - A Multi Channel TDC/ADC ASIC for SiPM Readout
        We present a multi channel ASIC developed mainly for the readout of Silicon Photomulipiers. Each of the 36 channels contains a single ended and a differential frontend, self triggered hit detection and time stamping with 50ps bin width, signal integration, digitization and a common fast serial readout. Several additional features like neighbor triggering or fast self-abort for noise hits or insufficient amplitude are included. The chip uses bump bonding and requires very few external components so that very compact modules can be constructed.
        Speaker: Ilaria Sacco
        Paper
        Slides
      • 131
        SamPic0: a 16-channel, 10-GSPS TWDC digitizer chip for picosecond time tagging
        SamPic0 is a Time and Waveform to Digital Converter (TWDC) multichannel chip. Each of its 16 channels associates a DLL-based TDC providing a raw time with an ultra-fast analogue memory allowing fine timing extraction as well as other parameters of the pulse. Each channel also integrates a discriminator that can trigger it independently or participate to a more complex trigger. After triggering, the analogue data are digitized by an on-chip ADCs and only those corresponding to a region of interest are sent serially to the acquisition. The paper describes the detailed SAMPIC0 architecture and reports its main measured performances.
        Speaker: Herve Marie Xavier Grabas (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
        Slides
      • 132
        ROC chips for imaging calorimetry at the International Linear Collider
        Imaging calorimetry at the International Linear Collider requires highly granular and innovative detectors. Technological prototypes have been built and tested under the CALICE collaboration framework and FP6 EUDET, FP7 AIDA EU programs. These prototypes are readout by multi-channel chips named SKIROC2, SPIROC2 and HARDROC2, designed in SiGe 350 nm technology by the IN2P3 OMEGA group. In this presentation, the ASIC architectures and test results on test bench and at system level will be described as well as first results of test bench measurements performed on HARDROC3, which is the first of the “3rd generation” chip to be submitted and where the 64 channels are handled independently to perform zero suppress on chip.
        Speaker: Nathalie Seguin-Moreau (U)
        Paper
        Slides
      • 133
        Petiroc and Citiroc : Front-end ASICs for SiPM read-out and ToF applications
        Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out. Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement. Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps). Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs. Timing measurement down to 7 ps RMS jitter for Petiroc and 100ps RMS for Citiroc is possible along with 1 % linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 2mW/channel for Citiroc, excluding ASICs outing buffer.
        Speaker: Julien Fleury (Weeroc)
        Paper
        Slides
    • Programmable logic, design tools and methods: A6 Town Hall, Congress Center

      Town Hall, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Magnus Hansen (CERN)
      • 134
        Soft Error Rate Estimations of the Kintex-7 FPGA within the ATAS Liquid Argon Calorimeter
        There is great interest in using Field Programmable Gate Arrays (FPGAs) within high-energy physics experiments due to their reconfigurability, ease of use, and support for high-speed serial I/O. SRAM-based FPGAs, however, are susceptible to radiation induced single event upsets. This paper estimates the soft-error upset rate of the Kintex-7 FPGA within the ATLAS Liquid Argon Calorimeter environment. Radiation experiments were performed on this device at the Los Alamos Neutron Science Center and the H4 beam line at CERN. Results from these experiments suggest that while single event upsets are present, they can be addressed with appropriate SEU mitigation techniques.
        Speaker: Helio Takai (Brookhaven National Laboratory (US))
        Slides
      • 135
        10Gbps TCP/IP streams from the FPGA for the CMS DAQ Eventbuilder Network
        For the upgrade of the DAQ of the CMS experiment in 2013/2014 an interface between the custom detector Front End Drivers (FEDs) and the new DAQ eventbuilder network has to be designed. For a loss-less data collection from more then 600 FEDS a new FPGA based card implementing the TCP/IP protocol suite over 10Gbps Ethernet has been developed. We present the hardware challenges and protocol modifications made to the TCP in order to simplify its FPGA implementation together with a set of firmware and hardware tests and performance measurements which were carried out with the current prototype. The measurements include tests of TCP stream aggregation and congestion control.
        Speaker: Petr Zejdl (CERN)
        Paper
        Slides
      • 136
        APEnet+ 34 Gbps Data Transmission System and Custom Transmission Logic.
        APEnet+ is a point-to-point, low-latency, 3D-torus network controller integrated in a PCIe Gen2 board based on Altera Stratix IV FPGA. We characterize the transmission system (embedded transceivers driving external QSFP+ modules), analyzing signal integrity, throughput, latency, BER and jitter at different data-rate up to 34Gbps. We estimate the efficiency of custom logic able to sustain 2.6 GB/s per link with a memory consumption of 40KB, guaranteeing deadlock free routing and systemic awareness of faults. Finally, we show the preliminary results obtained with next-generation FPGA embedded transceivers and propose a new protocol to increase the performance with the same memory consumption.
        Speaker: Andrea Biagioni (INFN)
        Paper
        Slides
      • 137
        A Real-time Histogramming Unit for Luminosity and Beam Background Measurements for each Bunch Crossing at the CMS Experiment
        The Real-time Histogramming Unit (RHU) is a VME board for sampling and processing discriminated signals from detectors in real time and free of dead-time. The RHU is used at the CMS experiment to measure the arrival time of signals from the BCM1F detectors relative to the orbit trigger of the LHC at CERN. The RHU incorporates a FPGA, 21MBit memory and an embedded Linux system for readout. For each input channel a histogram is produced by the FPGA algorithm in real time that contains the hits per bunch over several orbits. A postmortem buffer can be used for data analysis after a beam dump.
        Speaker: Marek Penno (Deutsches Elektronen-Synchrotron (DE))
        Slides
    • 4:30 PM
      Break
    • Microelectronics User Group Trumpet 3, Congress Center

      Trumpet 3, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Kostas Kloukinas (CERN)
      • 138
        News on foundry access services via CERN
        Speaker: Kostas Kloukinas (CERN)
        Slides
      • 139
        Status of CMOS 65nm technology access, distribution and IP blocks development
        Speaker: Sandro Bonacini (CERN)
        Slides
      • 140
        Open discussions
    • Optoelectronics Working Group Room, Congress Center

      Room, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy

      The Opto Working Group will review the status of four optoelectronics projects: GBT, Versatile Transceiver, LOC and US-CDRD. In the first part of the meeting, attendants will get an overview of the on-going work and will participate to a discussion on the status and evolution of these projects. In the second part of the meeting, progress with the evaluation of Silicon-photonics in our community will be presented and its potential will be discussed.

      Convener: Francois Vasey (CERN)
    • Power Working Group Cool, Congress Center

      Cool, Congress Center

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Magnus Hansen (CERN)
      • 147
        Powering large FPGAs - ALTERA
        Speaker: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))
        Slides
      • 148
        Powering large FPGAs - XILINX
        Speaker: Andrew William Rose (Imperial College Sci., Tech. & Med. (GB))
        Paper
        Slides
      • 149
        A reliability test system for production grade DC-DC modules
        Speaker: Isaac Troyano Pujadas (CERN)
        Slides
      • 150
        Discussion
    • xTCA Working Group Trumpet 1

      Trumpet 1

      Perugia, IT

      <font face="Verdana" size="2.5">Congress center Giò Via R. D'Andreotto, 19 06124 Perugia (PG) Italy
      Convener: Markus Joos (CERN)
      • 151
        Evaluation results from AC/DC converters for xTCA
        Speaker: Vincent Bobillier (CERN)
        Slides
      • 152
        Summary of evaluation results of xTCA equipment
        Speaker: Matteo Di Cosmo (Ministere des affaires etrangeres et europeennes (FR))
        Slides
      • 153
        Messages from our friends
        Speaker: Markus Joos (CERN)
        Slides
      • 154
        ATCA developments for the ATLAS Tile Calorimeter upgrade
        Speaker: Fernando Carrio Argos (Universidad de Valencia (ES))
        Slides
      • 155
        Update on the ATCA/AMC readout cards for LHCb
        Speaker: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))
        Slides
      • 156
        Update on the AMC13 project in CMS
        Speaker: Eric Shearer Hazen (Boston University (US))
        Slides
      • 157
        SlinkXpress
        Speaker: Attila Racz (CERN)
        Slides
    • Plenary 7: Vertically Integrated Circuits
      Convener: Ken Wyllie (CERN)
      • 158
        3D Integration, from tool box to applications
        After a tremendous technology modules development phase, 3D integration is now looking for the right use cases. Miniaturization and bandwidth needs are partially addressed by 2,5D heterogeneous interposers, but with limited impacts on competitiveness and cost. Disruptive 3DIC stacking is potentially offering unmatched performances and scalability in both niche and consumers markets but is facing difficult integration challenges in terms of signal integrity, thermal/mechanical managements and reliability. Specific applications oriented technological solutions are today required and will be reviewed in this talk. We will discuss how microelectronic for particle physics and imaging is about to become one of the main driver and recipient of 3D integration.
        Speaker: Yann Lamy (CEA- LETI)
        Slides
    • TOPICAL (Packaging & High Density Hybrids): First Part
      Convener: Ken Wyllie (CERN)
      • 159
        Microfabricated silicon on-detector cooling systems
        Microfabrication technologies are being investigated by the PH/DT group at CERN for optimized, localized on-detector cooling solutions for silicon tracking systems. Silicon microchannel cooling has been selected for the active thermal management of the NA62 GTK pixel detectors. 130 µm thick silicon plates with embedded microchannels, in which the radiation hard liquid C6F14 flows, are thermally interfaced to the backside of the FE chips. This technology has been demonstrated to be advantageous in terms of cooling efficiency, material reduction and suppression of any CTE mismatch problem. Following this first successful application, further studies have been launched on two-phase flow for the upgrades of the ALICE ITS and the LHCb VeLo detectors.
        Speaker: Alessandro Mapelli (CERN)
        Slides
      • 160
        Hybrid circuit prototypes for the CMS Tracker upgrade front-end electronics
        New high-density interconnect hybrid circuits are under development for the CMS tracker modules at the HL-LHC. These hybrids will provide module connectivity between flip-chip front-end ASICs, strip sensors and a service board for the data transmission and powering. Rigid organic based substrate prototypes and also a flexible hybrid design have been built, containing up to eight front-end flip chip ASICs. A description of the function of the hybrid circuit in the tracker, the first prototype designs, results of some electrical and mechanical properties from the prototypes, and examples of the integration of the hybrids into detector modules are presented.
        Speaker: Georges Blanchot (CERN)
        Paper
        Slides
    • 10:35 AM
      Break
    • TOPICAL (Packaging & High Density Hybrids): Second Part
      Convener: Ken Wyllie (CERN)
      • 161
        The Front-End Hybrid for the ATLAS HL-LHC Silicon Strip Tracker
        For the HL-LHC, ATLAS will install a new all-silicon tracking system. The strip part will comprise five barrel layers and seven end caps on each side. The detectors will be connected to highly-integrated low-mass front-end electronic hybrids with custom-made ASICs in 130nm technology. The hybrids are flexible PCB four-layer copper polyimide constructions. They are designed and populated at the Universities involved, while the flex PCB is produced in industry. This presentation will describe the evolution of hybrid designs for the barrel and endcap, discuss their electrical performance, and present results from reading out prototype modules made with the hybrids.
        Speaker: Kambiz Mahboubi (Physikalisches Institut, Universitaet Freiburg)
        Paper
        Slides
      • 162
        Ultra-thin packaging technologies for CMOS pixel sensors: embedding in kapton foils
        Monolithic CMOS Pixels (MAPS) integrate on the same silicon substrate the radiation sensor element with the processing electronics. Their thickness can be very small: typically less than 50 µm. This allows for very small material budget, if not spoiled by other mechanics elements. In order to demonstrate feasibility of large area, ultra-light sensor ladders (< 0.1% radiation length) based on MAPS, we develop novel packaging method. Thinned sensors are embedded in polymer (kapton) film, electrical connection to pads are implemented by aluminum deposition following by lithography steps (no wire bonding). Details of ladder design and electrical tests results are presented.
        Speaker: Wojciech Dulinski (Institut Pluridisciplinaire Hubert Curien (FR))
        Slides
    • WG Summaries
      • 163
        xTCA
        Speaker: Markus Joos (CERN)
        Slides
      • 164
        Optoelectronics Working Group Summary
        Speaker: Francois Vasey (CERN)
        Slides
      • 165
        Microelectronics User Group Summary
        Speaker: Kostas Kloukinas (CERN)
        Slides
      • 166
        Power Working Group Summary
        Speaker: Magnus Hansen (CERN)
        Slides
    • TWEPP-13 Close Out
      Conveners: Gian Mario Bilei (Universita e INFN (IT)) , Jorgen Christiansen (CERN)
      slides