Speaker
Description
Summary
The LHCb collaboration is currently preparing the upgrade of the experiment to allow, after 2018, an efficient data collection while running at an instantaneous luminosity of 2x1033/cm2s-1. The upgrade will permit 40 MHz detector readout, and events will be selected by means of a very flexible software-based trigger.
The muon system will be upgraded to allow the complete event readout at 40 MHz and to reduce the system dead-time in some regions of the apparatus that will become critical at the upgrade instantaneous luminosities.
The upgrade of the muon system will be performed in two phases. In the first phase the off-detector readout electronics will be redesigned to allow complete event readout at 40 MHz. The new boards (the new off-detector electronics boards, nODEs), compatible with the current ones to simplify installation, will incorporate a new VLSI rad-hard ASIC (nSYNC) that will perform muon hit time measurement, bunch-crossing synchronization, event frame generation and zero suppression functionalities. Both the non-zero suppressed muon hit information and the zero-suppressed hit time information will be sent via GBT optical links to the new LHCb readout boards, the so-called TELL40, which will perform the subsystem readout at 40 MHz. The TELL40 boards will be built according to the ATCA standard. Each board will host 4 AMC mezzanines, each one equipped with a high-end ALTERA Stratix V FPGA to provide data decoding, formatting, buffering and finally transmission to the high-level trigger farm via 10Gb Ethernet interface. The FPGA is so powerful that it will also allow the muon trigger algorithms to be implemented on it, simplifying the current system and making it more reliable.
In this first phase of the upgrade the boards used for the muon detectors front-end configuration (service boards, SB) and for the front-end pulsing for time alignment purposes (pulse-distribution module, PDM) will also be replaced with newer versions (respectively the nSB and the nPDM), to improve the detector configuration and monitoring speed and capabilities by making an optimal use of the bandwidth provided by the GBT links. The GBT-SCA ASIC will be used for this purpose, since it provides many digital interfaces that are compatible with the current muon detector front-end electronics.
Finally, in this first phase of the upgrade, part of the muon readout channel logical-ORs, performed by the so-called intermediate boards (IB) and used to reduce the total readout channel count in the current muon system, will be removed to reduce the dead-time in some already critical regions.
This first phase of the muon system upgrade will be completed by 2019, at the end of the LHC Long Shutdown 2 (LS2), to allow the LHCb operation at an instantaneous luminosity of 2x1033/cm2s-1.
Only in a successive phase, the muon group is considering the installation of higher-granularity detectors, able to operate at the very high particle rates of the upgrade, in particular in the most irradiated regions of the first muon stations. These new detectors, to be built using Triple-GEM technology, will replace the current Multi-Wire Proportional Chambers and will guarantee improved detector aging properties and reduced system dead-time, to allow an efficient muon system performance in the severe upgrade data taking conditions.
