Conveners
Poster: First Part
- Mitchell Franck Newcomer (University of Pennsylvania (US))
Poster: Second part
- Mitchell Franck Newcomer (University of Pennsylvania (US))
Juan Mauricio Ferre
(University of Barcelona (ES))
9/24/13, 5:00โฏPM
Poster
This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with a 4ps jitter and 18ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise...
Claudio Gotti
(INFN and Univ. of Milano Bicocca (IT))
9/24/13, 5:01โฏPM
Poster
The CLARO-SiGe is a prototype ASIC for single photon counting with
pixellated photomultipliers, designed to sustain a high counting rate at low power.
Each channel is made of a charge amplifier to readout the current
pulses on a low impedance node and a discriminator with a settable
threshold to count the pulses above threshold.
The architecture of the whole channel is differential.
The...
Elia Conti
(Universita e INFN (Perugia, IT))
9/24/13, 5:02โฏPM
Poster
The technical challenges related to increased collision rates of the LHC will significantly affect detector electronics design. Efficient hit processing is achieved in pixel detectors by grouping pixel chips in regions, which share buffering logic. We present an approach to determine an optimized sharing strategy between pixels, depending on the shape of clustered hits in the detector. Simple...
Miroslaw Firlej
(AGH University of Science and Technology (PL))
9/24/13, 5:03โฏPM
Poster
The design and measurements results of low power Phase-Locked Loop (PLL) prototype for applications in particle physics detectors readout systems are presented. The PLL fabricated in 130nm IBM technology was designed and simulated for frequency range 10MHz-3.5GHz. Internal voltage controlled oscillator (VCO) should work in 16 frequency ranges/modes, switched either manually or automatically....
Thanh Hung PHAM
(CNRS)
9/24/13, 5:04โฏPM
ASICs
Poster
Two designs of CMOS pixel sensor with in-pixel analog to digital conversion have been prototyped in a 0.18ยตm CIS process. The first design integrates a discriminator into each pixel within an area of 22ร33ยตm2 in order to meet the requirements of the ALICE-ITS upgrade. The second design features 3-bit charge encoding inside a 35ร35ยตm2 pixel which is motivated by the specification of the outer...
Tobias Harion
(Kirchhoff-Institut Heidelberg)
9/24/13, 5:05โฏPM
Poster
STiC is a mixed mode readout ASIC for Silicon-Photomultipliers developed in the UMC 180nm CMOS technology. The chip has been designed for the EndoToFPET-US project and aims at providing a high timing resolution to high energy physics and medical imaging applications. The signal is read out and discriminated by a dual threshold method. A low threshold discriminator provides a high precision...
Yunan Fu
(Univerisity of Bonn)
9/24/13, 5:06โฏPM
Poster
Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256 x 256 pixels organized in a square pixel-array with 55um pitch. Oscillators running at 640MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter...
yang You
(Southern Methodist University)
9/24/13, 5:07โฏPM
ASICs
Poster
We present single-event-hardened phase-locked loop for structured-ASIC and digital delay-locked loop for DDR2 memory interface applications. The PLL covers a frequency range from 12.5 MHz to 500 MHz with an RMS jitter of 4.7 pS. The DLL operates at 267 MHz and has a phase resolution of 60 pS. Designed in 0.13 ยตm CMOS technology, the PLL and the DLL are hardened against SEEs for charge...
Patrick Pangaud
(Centre National de la Recherche Scientifique (FR))
9/24/13, 5:10โฏPM
Poster
To face new challenges brought by the upgrades of the Large Hadron Collider at CERN and of ATLAS pixels detector, for which high spatial resolution, very good signal to noise ratio and high radiation hardness are needed, 3D Integrated Technologies are investigated. Commercial offers of such technologies are only very few and the 3D designer's choice is as a consequence strongly constrained. We...
Heiko Engel
(Johann-Wolfgang-Goethe Univ. (DE))
9/24/13, 5:21โฏPM
Poster
The ALICE experiment uses custom FPGA-based computer plug-in cards as interface between the optical readout link and the PC clusters of Data Acquisition (DAQ) and High-Level Trigger (HLT). The previous cards for DAQ and HLT have been developed as independent projects and are now facing similar problems with obsolete major interfaces and limited link speeds. A new common card has been developed...
Wilco Vink
(NIKHEF (NL))
9/24/13, 5:22โฏPM
Poster
The LHCb experiment studies B-decays at the LHC. The Outer Tracker straw tubes detects charged decay particles. The on-detector electronics will be upgraded to be able to digitize and transmit drift-times at every LHC crossing without the need for a hardware trigger. FPGAs have been preferred to application-specific integrated circuits to implement dead-time free TDCs, able to transmit data...
Nicola De Simone
(INFN Rome)
9/24/13, 5:23โฏPM
Poster
The NA62 experiment at CERN SPS aims to increase the precision in the measure of the Branching Ratio of the K+->pi+nu nubar decay. The required background suppression level due to the decay K+->pi+pi0 can be achieved, among the others, implementing the photon veto in the angular range [1,10] mrad by using a LKr calorimeter. This paper deals with the implementation of the LKr L0 trigger peak...
Dimitrios Marios Kolotouros
(University of Ioannina (GR))
9/24/13, 5:34โฏPM
Poster
A new generation FPGA-based Timing-Trigger and Control (TTC) system based on emerging Passive Optical Network (PON) technology is being investigated to potentially replace the existing off-detector TTC system used by the LHC experiments. The new system must deliver trigger and data with low and deterministic latency as well as a recovered bunch clock with picosecond-level jitter. It also...
Alexander Paramonov
(Argonne National Laboratory (US))
9/24/13, 5:35โฏPM
Poster
We report on the development of a new commercial off-the-shelf optical transceiver as a candidate for the transmission of data from the detector to the counting room for experiments at the Large Hadron Collider (LHC). The device is manufactured by Molex using CMOS integrated silicon photonics developed by Luxtera. A transceiver contains four RX and four TX channels operating at 10 Gbps each,...
Todd Brian Huffman
(University of Oxford (GB))
9/24/13, 5:36โฏPM
Poster
We present results on all aspects of fibre reliability after exposure to the expected doses at HL-LHC. The results for the cold Radiation Induced Attenuation (RIA) are reviewed. The results of new studies of the effect of radiation on fibre bandwidth and mechanical reliability are presented. The fibre bandwidth was studied using measurements of chromatic dispersion and Differential Mode Delay...
Chonghan Liu
(Southern Methodist University)
9/24/13, 5:37โฏPM
Poster
We present a small-footprint dual-channel optical transmitter module called MTx for the High-Luminosity LHC experiments. The MTx module consists of two separate commercial transmitter optical sub-assemblies (TOSAs) and a dual-channel laser driver ASIC. We have demonstrated that the module prototypes can operate at 10 Gbps using commercial 10 Gbps laser diode drivers. We are developing an 8...
Sarah Seif El Nasr
(University of Bristol (GB))
9/24/13, 5:38โฏPM
Poster
We report on the results of a radiation test carried out using 20 MeV neutrons on optoelectronic components, such as multi-channel transmitters and Si photonics building blocks, for use in future-data transmission links by experiments at the High-Luminosity LHC.
Ivo Polak
(Acad. of Sciences of the Czech Rep. (CZ))
9/24/13, 5:39โฏPM
Poster
We report on electronic design of new calibration and monitoring system developed for the scintillator tiles calorimeter (AHCAL) for the ILC. System is based on original fast (3 ns pulsewidth) and precise LED driver called QMB. LED driver uses unique Quasi-Resonant circuit with embedded toroidal inductor. The QR-LED driver creates sinusoidal pulse to drive the LED. It has high dynamic range of...
Agostino Lanza
(INFN Pavia (IT))
9/24/13, 5:50โฏPM
Poster
Prototypes of DC/DC converters were designed and built with the aim of satisfying the foreseen working parameters in the Phase 2 LHC experiments, using both MOSFETs and more recent devices like SiC and GaN transistors. Optimization of their design, based on the comparison between the simulated and measured thermal, electrical and mechanical performance, is in progress, and many improvements...
Waclaw Karpinski
(Rheinisch-Westfaelische Tech. Hoch. (DE))
9/24/13, 5:51โฏPM
Poster
A novel powering scheme based on the DC-DC conversion technique will be exploited to power the CMS Phase-1 pixel detector. DC-DC buck converters for the CMS pixel project have been developed, based on the AMIS5 ASIC by CERN. We will show the performance of these devices, including efficiency and line and load regulation at various temperatures. Reliability studies based on a preseries of 200...
Ahmed Bassalat
(Universite de Paris-Sud 11 (FR))
9/24/13, 5:52โฏPM
Poster
During the shutdown 2013/14, for the enhancement of the current ATLAS Pixel Detector a fourth layer (Insertable B Layer, IBL) consisting of 14 staves is being built and will be installed between the innermost layer and a new beam pipe. A new read out chip
generation has been developed and two different sensor designs, a rather conventional planar
and a 3D design, have been flip chipped to...
Giovanni Mazza
(INFN sez. di Torino)
9/24/13, 6:00โฏPM
Poster
The Silicon Pixel Detector (SPD) of the PANDA experiment is the closest one to the interaction point and therefore the sensor and its electronics are the most exposed to radiation. The Total Ionizing Dose (TID) issue has been addressed by the use of a deep-submicron technology (CMOS 0.13 um) for the readout ASICs. While these technology are very effective in reducing radiation induced oxide...
Alessandro Bartoloni
(Universita e INFN, Roma I (IT))
9/24/13, 6:01โฏPM
Poster
The CMS Electromagnetic Calorimeter (ECAL) has played a vital role in the discovery of the Higgs Boson and other physics requiring the precise detection and measurement of electrons and photons. It is a homogenous lead tungstate scintillating crystal calorimeter with on-detector electronics based mainly on CMOS 0.25um ASICs and rad-hard gigabit optical links. The ECAL provides sums of energy...
Christian Faerber
(Ruprecht-Karls-Universitaet Heidelberg (DE))
9/24/13, 6:02โฏPM
Poster
This paper describes radiation studies of SRAM-based FPGAs as a central component of the electronics for a possible upgrade of the LHCb Outer Tracker readout electronics to a frequency of 40 MHz. Two Arria GX FPGAs were irradiated with 20 MeV protons to radiation doses of up to 7 Mrad. During and between the irradiation periods the different FPGA currents, the package temperature, the...
Frederic Bruno Magniette
(Ecole Polytechnique (FR))
9/24/13, 6:11โฏPM
Poster
A DAQ system is developped within the SiW Ecal CALICE collaboration. It provides a flexible and scalable architecture, compound of three parts. A detector interface (DIF) extracting data from frontend electronics and sending them as packets. Two levels of data concentration, control clock and fast command fanout. The two cards, named DCC and GDCC, use respectively FastEthernet and...
Daniel Esperante Pereira
(Universidad de Valencia (ES))
9/24/13, 6:12โฏPM
Poster
Active pixels sensors based on the DEPFET technology will be used for the innermost vertex detector of the future Belle-II experiment. The increased luminosity of the e+e- SuperKEKB collider entails challenging detector requirements, namely: low material budget, low power consumption, high precision and efficiency, and a huge readout rate. The DEPFET active pixel technology has shown to be the...
Stefano Meroli
(Universita e INFN (IT))
9/24/13, 6:13โฏPM
Poster
The consolidation and upgrade of the cabling infrastructure of the CERN accelerator complex is one of the most critical activities of the LHC Long Shutdown 1. This implies an extraordinary challenge in terms of project management, resource and activity planning, quality control and manpower organization. About 1000 km of both copper and optical fiber control cables have to be newly installed...
Michele Caselle
(Karlsruhe Institute of Technology)
9/24/13, 6:14โฏPM
Poster
The recording of coherent synchrotron radiation requires DAQ systems with high temporal resolution. To resolve ultra-short terahertz pulses emitted by single bunch YBCO superconducting thin film detectors have been developed. A novel data acquisition system for sampling of the individual ultra-short terahertz pulses with high accuracy and real-time data processing is presented. The DAQ system...
Pablo Moreno
(Universidad de Valencia)
9/24/13, 6:15โฏPM
Poster
TileCal is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider at CERN. The main upgrade of the LHC to increase the instantaneous luminosity is scheduled for 2022. The High Luminosity LHC, also called upgrade phase-2, will imply a complete redesign of the read-out electronics in TileCal. In the new read-out architecture, the front-end electronics aims to...
Dedalo Marchetti
(Universita' di Roma Tre)
9/24/13, 6:16โฏPM
Poster
Cosmology studies call for accurate measurements of cosmic microwave background radiation anisotropies. A promising technique to achieve the required precision is based on big arrays of Kinetic Inductance Detectors (KID). In this paper, we describe, a new strategy to stimulate and read a KID array of 128 pixels based on FPGAs and analog to digital converters. The project can reach an analog...
Alessandro Cardini
(Universita e INFN (IT))
9/24/13, 6:17โฏPM
Poster
The LHCb collaboration is currently working on the upgrade of the experiment to allow, after 2018, an efficient data collection while running at an instantaneous luminosity of 2x1033/cm2s-1. The upgrade will allow 40 MHz detector readout, and events will be selected by means of a very flexible software-based trigger. The muon system will be upgraded in two phases. In the first phase, the...
Thomas Lenzi
(Universite Libre de Bruxelles (BE))
9/24/13, 6:18โฏPM
Poster
For the LHC high luminosity phases new triple-GEM detectors should be installed in the CMS muon endcap spectrometer, together with a new readout system. The functional requirements on the system are to provide both triggering and tracking information. In addition the system will be designed to take full advantage of current generic developments introduced for the LHC upgrades: CERN GLIB boards...
Lorne Levinson
(Weizmann Institute of Science (IL))
9/24/13, 6:19โฏPM
Poster
The current off-chamber readout chain in the ATLAS experiment consists of sub-detector specific ReadOut Drivers (RODs), typically 9U VME cards, which receive data from a number of front-end links. The RODs build event fragments and forward these via point-to-point links, the Read-Out Links (ROLs) to the ReadOut System (ROS). The functionality of the RODs, not only consisting of fragment...
Rui Gao
(University of Oxford (GB))
9/24/13, 6:20โฏPM
Poster
The TORCH detector is proposed for the low-momentum particle identification upgrade of the LHCb experiment. It combines Time-Of-Flight and Cherenkov techniques to achieve positive ฯ/K/p separation up to 10GeV/c. This requires a timing resolution of 70ps for single photons. This paper will report on the electronics developed for such measurements, using commercial Micro Channel Plate devices...
Mikhail Matveev
(Rice University)
9/24/13, 6:25โฏPM
Poster
We report the results of our efforts in the past year to upgrade the Cathode Strip Chamber (CSC) Muon Sorter at CMS. After presenting an overview of the existing CSC Track Finder hardware and upgrade requirements we describe the modification of the existing board and transition to a new Muon Sorter. Then we discuss the improved sorting algorithm and its inplementation in firmware. Current...
Jamieson Olsen
(Fermilab)
9/24/13, 6:26โฏPM
Poster
High luminosity conditions at the LHC pose many unique challenges for potential silicon based track trigger systems. Among those challenges is data formatting, where hits from thousands of silicon modules must first be shared and organized into overlapping eta-phi trigger towers. Communication between nodes requires high bandwidth, low latency, and flexible real time data sharing, for which a...
Matthias Gorzellik
(Albert-Ludwigs-Universitaet Freiburg (DE))
9/24/13, 6:27โฏPM
Poster
The GANDALF framework has been developed to deliver a high precision, high performance detector readout and trigger system for particle-physics-experiments such as the COMPASS-II experiment at CERN. Combining the high performance pulse digitization and feature extraction capabilities of twelve GANDALF modules, each comprising a Virtex-5 SX95T, with the strong computation power of a Virtex-6...
200.
NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs.
Alessandro Lonardo
(Universita e INFN, Roma I (IT))
9/24/13, 6:28โฏPM
Poster
The adoption of GPUs in the low level trigger systems is currently being investigated in several HEP experiments.
While GPUs show a deterministic behaviour in performing computational
tasks, data communication is the main source of fluctuations in the response time of such systems.
We designed NaNet, a FPGA-based NIC supporting 1/10GbE links and the custom 34 Gbps APElink channel.
The...
Krzysztof Piotr Swientek
(AGH University of Science and Technology (PL))
9/25/13, 4:35โฏPM
Poster
The LHCb detector, operating at the LHC proton-proton collider, has finished its Run I period. After more than two years of collision data taking the experiment accumulated corresponding integrated luminosity of around 3.1 fb-1. The full recorded data sample will be used by physicsts to search for New Physics and precise measurement of CP-violation in heavy flavor quark sector. Despite its...
Tuomas Sakari Poikela
(University of Turku (FI))
9/25/13, 4:36โฏPM
Poster
In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256x256 pixels with a pixel pitch of 55um.
The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured...
Filip Francis Tavernier
(CERN)
9/25/13, 4:37โฏPM
Poster
A clock and data recovery IP, the eCDR, is presented which is intended to be implemented on the detector front-end ASICs that need to communicate with the GBTX by means of e-links. The programmable CDR accepts data at 40, 80, 160 or 320 Mbit/s and generates retimed data as well as 40, 80, 160 and 320 MHz clocks that are aligned to the retimed data. Moreover, all the outputs have a programmable...
Tobias Harion
(Kirchhoff-Institut Heidelberg)
9/25/13, 4:38โฏPM
Poster
KLauS is an ASIC produced in the AMS 350nm SiGe process to read out the charge signals from silicon photomultipliers.
Developed as an analog frontend for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration,
the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with a high precision.
In order to...
Samuel Pierre Manen
(Univ. Blaise Pascal Clermont-Fe. II (FR))
9/25/13, 4:39โฏPM
Poster
The ALICE Collaboration at the CERN-LHC has
started a vast program of upgrades of the detector in the context
of the increase of the luminosity of the LHC from 2018 on. The
present very front-end electronics (VFE) of the Muon Trigger,
whose acronym is ADULT, must be replaced to limit the aging
of the Resistive Plate Chambers (RPCs) in the future expected
operating conditions. For this...
Piotr Kapusta
(Institute of Nuclear Physics PAN, Krakow (PL))
9/25/13, 4:41โฏPM
Poster
We present the prototype pixel detector built in the Silicon on Insulator (SOI) technology. The sensor matrix contains 1024 integrating type cells, read continuously out as a serial analog signal. The pixels are protected from the back-gate effect by the Buried P-Well implantations. Measured ENC value was found to be 130 electrons at 100us integration time. An on-chip prototype SAR ADC and a...
Philipp Schwegler
(Max-Planck-Institut fuer Physik (Werner-Heisenberg-Institut) (D)
9/25/13, 4:42โฏPM
Poster
New ATLAS Monitored Drift Tube (MDT) chambers with reduced tube diameter (sMDT) - 15 mm instead of 30 mm - have been developed for LHC luminosity upgrades. The shorter lengths of the pulse trains due to the smaller tube diameter allow to operate the sMDTs at much higher rates, however the gain in efficiency is limited by the shaping scheme of the current ASD (Amplifier-Shaper-Discriminator)...
Jim Hoff
(Fermilab)
9/25/13, 4:43โฏPM
Poster
Associative memory based track finding has been proven to provide a unique solution to fast silicon-based track trigger in the hadron collider environment. Future LHC experiments will demand greater speed and more patterns. While it is unlikely that scaling of 2D technology will satisfy the needs in a cost effective way, 3D Vertical Integration offers the possibility of dramatic improvements....
Eva Vilella-Figueras
(Universitat de Barcelona)
9/25/13, 4:44โฏPM
Poster
A monolithical GAPD (Geiger-mode Avalanche PhotoDiode) detector aimed to particle tracking at future linear colliders is being developed. A first prototype of a bidimensional GAPD pixel array has been designed and fabricated with a conventional 0.35 ยตm HV-CMOS process. The experimental characterization of the device shows that the expected noise counts generated by the sensor can be reduced to...
Andreas Neiser
(Institute of Nuclear Physics, Mainz - Germany)
9/25/13, 4:55โฏPM
Poster
The TRB3 features four FPGA-based TDCs with <20ps RMS time precision
between two channels and 256+4+4 channels in total. One central FPGA
provides flexible trigger functionality and GbE connectivity including
powerful slow control. We present recent users' applications of this
platform following the COME&KISS principle: Successful test beamtimes
at CERN (CBM), in Juelich and Mainz with an...
Sven Schatral
(University of Heidelberg)
9/25/13, 4:58โฏPM
Poster
The Compressed Baryonic Matter experiment at FAIR in Darmstadt has special requirements on the Data Acquisition Network. One of them is deterministic latency of all links from the back-end to the front-end, which enables synchronization in the whole read-out tree. Since front-end electronics (FEE) contains mixed-signal circuits for processing of detector raw data, special ASICs were developed....
Paolo De Remigis
(INFN)
9/25/13, 5:09โฏPM
Poster
The upgrade of the second level electronics of the muon Drift Tube (DT) in CMS is focused on improving the electronic system to maintain its reliability at High Luminosity LHC. The project foresees the relocation of the Sector Collector electronics from the CMS cavern to the counting room. The system requires an electrical to optical conversion operated by the Copper to Optical Fibre (CUOF)...
Rainer Schwemmer
(CERN)
9/25/13, 5:10โฏPM
Poster
The LHCb experiment will upgrade its DAQ system to a trigger less, 40MHz read-out after LS2. To be able to process the approximately 40Tbit/s of data we will require a massive computing farm. This computing farm can not be installed underground, in the vicinity of the detector anymore due to the enormous power and cooling requirements. An affordable data transport solution has to be found to...
Jingbo Ye
(Southern Methodist University (US))
9/25/13, 5:11โฏPM
Poster
The integration of VCSEL array and driving ASICs in a custom optical transmitter module (ATx) for operation in the detector front-end is demonstrated. The ATx provides 12 parallel channels with each channel operating at 10 Gbps. The assembly comprises a ceramic substrate with high-density wiring for electrical interface, OE components, and a micro-lens array with guiding structure for optical...
Jan Troska
(CERN)
9/25/13, 5:12โฏPM
Poster
Production of the Versatile transceiver and twin transmitter modules for use in the readout and control systems of upgrading LHC detector systems is starting. We review the performance of the prototypes produced so far and show that the modules are ready for production. We outline the commercial actions being taken to procure parts and assemblies and show the production plan for delivering...
Alfonso Tarazona Martinez
(Valencia Polytechnic University (ES))
9/25/13, 5:13โฏPM
Poster
Upgrades of the LHC detectors target significantly higher event rates and higher bandwidth over custom links which transmit data, trigger, clock and control (DTCC) between the front-end and the readout units. We report on a DTCC point-to-point link protocol designed to work over 8B/10B encoding with 2 or 4 pair copper implementation or over optical fiber. A version of the DTCC protocol over...
Ludovic Eraud
(LPSC,Centre National de la Recherche Scientifique (FR))
9/25/13, 5:24โฏPM
Poster
Abstract :
The environment conditions of the Long Duration Balloon flight are the worst possible for high voltage electronics which must survive at the altitude of 40km and a pressure of 5mbar in the Payload of the CREAM (COSMIC Ray Energy And Mass) balloon. Three different high voltage power supplies (1400V, 2000V and 12000V with a maximum consumption of 20 mA per module) were developed at...
A A Hasib
(University of Oklahoma (US))
9/25/13, 5:25โฏPM
Power
Poster
High common mode offset voltages can arise in the ATLAS Pixel detector module communication links that could prevent new Pixel Detector modules from taking data because of the present grounding and power supply schemes. Isolation of all the detector module electronics supply channels eliminates this risk. We propose that it is possible to provide inexpensive, reliable and serviceable power...
Stefano Venditti
(Sezione di Pisa (IT))
9/25/13, 5:36โฏPM
Poster
The NA62 experiment at the CERN SPS (Super Proton Synchrotron) accelerator aims at studying ultra-rare kaon decays. The high resolution Liquid Krypton (LKr) calorimeter, built for the NA48 experiment, is a crucial part of the NA62 photon-veto system. However, the back-end electronics of the LKr calorimeter has to be redone in order to accommodate the new requirements. The exhaustive...
Gary Drake
(Argonne National Laboratory (US))
9/25/13, 5:37โฏPM
Poster
The CMS Hadron Calorimeter (HCAL) is scheduled to be upgraded to increase longitudinal depth segmentation in the Barrel and Endcap regions and to improve anomalous signal rejection efficiency in the Forward Region. ย In order to achieve these goals, the phototransducers and the front-end and back-end electronics of the HCAL will be upgraded in stages over the next several years. ย New PMTs in...
Nikolaos Trikoupis
(CERN)
9/25/13, 5:49โฏPM
Poster
For the next LHC run it is required to install 200 W of heating capacity to regenerate the beam screen by desorption of gas trapped on its walls. In the LHC, there are 272 beam screen heaters and the associated electronics limits the heating capacity to 25 W. These electronics are mostly installed inside the LHC tunnel and exposed to its radiation environment.
This paper describes the basic...
Johan Alme
(Bergen University College (NO))
9/25/13, 5:51โฏPM
Poster
This paper will present and discuss measurement results of single event upsets in the readout control FPGA of the ALICE Time Projection Chamber during the first LHC running period. The measurements have been performed during stable beam conditions for proton-proton, proton-lead and lead-lead collisions.
William Vigano
(CERN)
9/25/13, 6:01โฏPM
Poster
A wide range current digitizer card is needed for the acquisition module of the beam loss monitoring systems in the CERN Injector Complex. The fully differential frequency converter allows measuring positive and negative input currents with a resolution of 31nA in an integration window of 2ยตs. Increasing the integration window, the dynamic range covers 2โข1010 were the upper part of the range...
Matevz Cerv
(CERN)
9/25/13, 6:02โฏPM
Poster
The Diamond Beam Monitor (DBM) is a pCVD diamond pixel tracker for detecting high-energy charged particles. It is planned to be installed in the ATLAS experiment at CERN for the luminosity measurements. In this talk, the overview of the DBM system and the operation of the diamond pixel sensors are described.
Gregory Pigny
(CERN)
9/25/13, 6:03โฏPM
Poster
The 26 km of vacuum chambers where circulates the beam of LHC (Large Hadron Collider) must be maintained under UHV (Ultra High Vacuum) to minimize the beam interaction with residual gases, and allow the operation of specific systems. The vacuum is measured by several thousands of gauges along the accelerator. Bad vacuum measurements may trigger a beam dump and close the associated sector...
Fernando Carrio Argos
(Universidad de Valencia (ES))
9/25/13, 6:04โฏPM
Poster
The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux...
Eric Shearer Hazen
(Boston University (US))
9/25/13, 6:05โฏPM
Poster
The AMC13 provides clock, timing and DAQ service for many subdetectors
and central systems in the upgraded CMS detector. This year we have
developed an upgraded module, the AMC13XG, which supports 10 gigabit
optical fiber and backplane interfaces. Many of these modules are now
being installed in the CMS experiment during the current LHC shutdown.
We describe the implementation using...
Peyton Rose
(University of California,Santa Cruz (US))
9/25/13, 6:06โฏPM
Poster
In the event of beam loss at the LHC, ATLAS inner detector components nearest the beamline may be subjected to unusually large amounts of radiation. Understanding their behavior in such an event is important in determining whether they would still function properly. We built a SPICE model of the silicon strip module electrical system to determine the behavior of its elements during a realistic...
Thierry Caceres
(LAL Orsay)
9/25/13, 6:07โฏPM
Poster
A complex readout electronic chain has been designed for the EUSO-Balloon project. It contains two elements: the EC units (9 of them) and the EC-ASIC boards (6). The EC unit includes 64-channel Multi-Anode Photomultipliers and a set of pcbs used to supply the 14 different high voltages needed by the MAPMTs and to read out the analog output signals. These signals are transmitted to the EC-ASIC...
94.
Performance evaluation of multiple (16 channels) sub-nanosecond TDC implemented in low-cost FPGA
Georgios Konstantinou
(National Technical Univ. of Athens (GR))
9/25/13, 6:08โฏPM
Poster
NA62 experiment Straw tracker frontend board serves as a gas-tight detector cover and integrates two CARIOCA chips, a low cost FPGA (Cyclon III, Altera) and a set of 400Mbit/s links to the backend. The FPGA houses 16 sub-nanosecond resolution TDCs with derandomizers and an output link serializer. Evaluation methods, including simulations, and performance results of the system in the lab and on...
Juan Mauricio Ferre
(University of Barcelona (ES))
9/25/13, 6:09โฏPM
Poster
The LHCb collaboration foresees a major upgrade of the detector for the high luminosity run that should take place after 2018. Apart from the increase of the instantaneous luminosity at the interaction point of the experiment, one of the major ingredients of this upgrade is a full readout at 40MHz of the sub-detectors and the acquisition of the data by a large farm of PC. The trigger will be...
Jay Chapman
(University of Michigan, Ann Arbor, Michigan, 48109, USA)
9/25/13, 6:21โฏPM
Poster
A Verilog Behavioral simulation of sTGC trigger will be presented based on the current baseline concept with particular focus on the Level 1 latency obtained. Data for this trigger is taken from detector simulations with Garfield and PSpice, current measurements made in the existing small wheel, and FLUGG simulation of the arrival times of hits at high luminosities. These simulations will...
Dinyar Rabady
(University of Vienna (AT))
9/25/13, 6:22โฏPM
Poster
To continue triggering with the current performance in the LHC Run 2 the Global Muon Trigger (GMT) of the CMS experiment will be reimplemented in a Virtex-7 card utilizing the uTCA architecture. The thus available high-capacity input as well as increased logic could be used to migrate the final sorting stage of each subsystem to the GMT. Additionally the GMT will calculate a muonโs isolation...
