Speaker
Description
Summary
Delay lines are commonly used in high energy physics experiments since synchronization is critical for such kind of applications. The operating principle of digital delay lines is very simple: the user can set an arbitrary delay and thus compensate the latency introduced, for example, by cables or fibers.
This paper describes the implementation of a SPI-programmable (Serial Peripheral Interface) 4 triple channel (12 clock outputs) delay line based on a Delay Locked Loop (DLL) and developed for the LHCb electromagnetic and hadronic calorimeter upgrade. The user can configure up to 25 different clock phases to cover the 25 ns LHC clock in 1ns steps. The DLL is adjusted by means of two control voltages: the former is automatically generated by the phase comparator and charge pump circuit, while the later is externally adjusted by the user. This dual adjustment provides an operating range of 17.45 to 39.88ns, wider enough to ensure that systematic process or environmental variations will not prevent working properly with the LHC clock. The differential design as well as the use of weak inverters to ensure 180º phase and the implementation in 0.35um technology favors the minimization Differential Non Linearity (DNL), which is equal to 18ps for each 1ns delay element.
Despite this delay line chip can operate in standalone mode, it will be integrated into the next LHCb calorimeter front-end ASIC (ICECAL) in the near future, and consequently, the stringent noise requirements of the ASIC analog components must be met by the digital components and thus by the delay line. Therefore, the fully differential design of the DLL aims to reduce the switching noise produced by delay lines. The use of double guard rings also decreases the noise propagation through the substrate. The clock jitter induced by transient noise is lower than 4ps.
Design methodology of this chip prototype is also determined by the radiation environment where DLLs will operate. ICECAL chips will be mounted on ECAL front-end boards (FEBs), located inside the LHCb cavern. Moreover, the energy increase of the LHC machine (from 7 to 14 TeV) will increase the potentially dangerous ionizing radiations and thus, the probability of suffering from single event effects. The design must tolerate SEUs, SETs and SELs. The probability of suffering SELs is reduced by increasing the distance between PMOS and NMOS transistors and inserting double guard rings between them, so that PMOS and NMOS transistors are confined inside islands of the same transistor type. SEUs are avoided by implementing Triple Modular Redundancy Registers to store the DLL configuration and fault tolerant Finite State Machine in the SPI Slave. Finally, reset signals are protected from SETs by means of glitch suppressors.
