Speaker
Frederic Bruno Magniette
(Ecole Polytechnique (FR))
Description
A DAQ system is developped within the SiW Ecal CALICE collaboration. It provides a flexible and scalable architecture, compound of three parts. A detector interface (DIF) extracting data from frontend electronics and sending them as packets. Two levels of data concentration, control clock and fast command fanout. The two cards, named DCC and GDCC, use respectively FastEthernet and GigaEthernet. A software suite (named Calicoes), for controlling DAQ, detector chips, acquiring data from GigaEthernet, decoding frontend readout to various formats and aggregating data. Overall architecture, performance in test beam and prospects for use with hundreds of thousands channels are discussed.
Primary author
Frederic Bruno Magniette
(Ecole Polytechnique (FR))
Co-authors
Franck Gastaldi
(LLR Polytechnique - CNRS/IN2P3)
Remi Jean Noel Cornat
(Ecole Polytechnique (FR))
