Speakers
Prof.
Hélène Tap
(Université de Toulouse INP LAAS)Dr
Olivier Bernal
(Université de Toulouse INP LAAS)
Description
In situ studies of the geospace environment, including space weather monitoring, is mainly based on the measurements of particles and fields. The particle content of the Earth’s magnetosphere is studied with electron and ion detectors in various energy ranges, from the cold and dense eV solar wind to the MeV radiation belts.
Here, the in situ high-energy (50 keV to 725keV) electron measurement is targeted. The design and development of space embedded electronic equipment require a specific approach. An Analog-Front-End (AFE) design methodology is proposed to optimize noise, bandwidth, consumption, crosstalk and radiation hardness performances of such AFEs for Si semiconductor detectors.
Firstly, it is necessary to perfectly understand the detector and propose an equivalent electrical model. With this aim, the GEANT4 simulator is used to model the various physical effects associated with particles interacting within the Si detector. The number of generated electron-hole pairs can thus be estimated as a function of the incident particle energy. Further, the main electrical characteristics of the sensor such as its charge collection time, its parasitic capacitance as well as its leakage current, can also be retrieved to correctly build an equivalent electrical model of the detector.
Then, the choice of the technology should take into account both the space mission duration and the radiation environment characteristics. In addition, the state of the art of radiation hardness by design (RHBD) methods shows in particular that for thin oxide thickness CMOS technology , Total Ionizing Dose (TID) effects are greatly reduced by tunneling mechanism. However, for such technologies, the sensitivity to Single Event Effects (SEE) is increased and the circuit dynamic range is reduced. For missions in low earth orbit, electronic systems must withstand a TID of 20 krad for a period of two years. The 0.35 µm CMOS technology can be chosen because it can naturally withstand more than 50 krad. Also, this technology works with a supply voltage of 3.3 V which allows a high enough dynamic range. Further, to protect circuits from latchups while using standard CMOS technologies, the extensive use of guard rings is required. In addition, to minimize crosstalk and improve power supply rejection, it is useful to use an isolated-well technology. This feature is usually provided by High Voltage (HV) technologies. Finally, a 0,35µm CMOS HV technology has been chosen.
Secondly, the designed AFE should quantify the amount of detected charges in order to reconstruct the electron energy spectrum. Consequently, the AFE should have a linear output response to ease the mapping charge-electron energy. The first step is to convert charge into a voltage using a charge preamplifier (CPA). The CPA consists of a transconductance amplifier (OTA) with a feedback capacitance Cf to perform the charge integration. Then, in order to improve the Signal-to-Noise Ratio (SNR), the CPA output voltage is filtered by a circuit called pulse shaper (PS). Therefore, the analog-to-digital converter (ADC) input signal noise is reduced, which thus decreases the detection threshold level and increases the AFE achievable precision.To save power as well as reduce the influence of any external parasitic signals, analog to digital conversions of the CPA+PS output should be performed within the same chip. Thus, each channel has the following architecture: a CPA+PS, a comparator with an adjustable threshold voltage level, a peak detector (PD) and an 8 bits Successive Approximations Register (SAR) ADC. To summarize, the CPA+PS converts the incident charge into a proportional voltage and the comparator detects if the incoming charge is higher or lower than the desired threshold level. Note that the minimum detection threshold level can be obtained by setting the threshold voltage of the comparator just above the noise floor. The PD is used to store the maximal peak value of the PS output voltage, which is proportional to the electron energy. This stored voltage is then digitized by the SAR ADC. A control logic block of the system is also designed to manage the communications between the blocks.
The ASIC tests have shown a charge-to-voltage conversion gain of 60 mV/fC for a charge range of 0.6 fC to 32 fC. The equivalent noise charge (ENC) is 3119 e- with an input parasistic capacitance of 40 pF while consuming 2.5 mW. The circuit can perform measurements up to a 650 kHz rate.The next step is to characterize the ASIC associated with the SC detector in a vacuum chamber. Furthermore, the TID and the SEE tolerances must also be evaluated.
Primary author
Dr
Florent Bouyjou
(CEA)
Co-authors
Prof.
Hélène Tap
(Université de Toulouse INP LAAS)
Prof.
Jean-André Sauvaud
(Université de Toulouse UPS IRAP)
Dr
Olivier Bernal
(Université de Toulouse INP LAAS)
