May 14 – 16, 2014
University of Pennsylvania
US/Eastern timezone

Hardware Implementation of FPGA based Level-1 Tracking

May 14, 2014, 3:00 PM
25' presentation + 5' for discussion

25' presentation + 5' for discussion

Oral presentation


Jorge Chaves (Cornell University (US))


This presentation describes a new approach for track reconstruction to be used in the Level 1 trigger. This is intended for the upgraded CMS all-silicon tracker, which is to be installed for the High Luminosity era of the LHC (HL-LHC). The track finding is seeded with pairs of hits from adjacent layers in the tracker that are combined to form 'tracklets'. The tracklets are projected to other layers (both outside-in and inside-out), where hits consistent with the trajectory of a high-pT track are added. The pT threshold for the tracks to be considered is 2 GeV. A linearized track fit provides the final 3-D track parameters. The strict timing requirements of the L1-trigger at CMS require that the fit is done within 5 us, which is within the estimates for the algorithm. The algorithm is such that allows for an integer implementation to be used on an FPGA. Currently we are working on a demonstrator hardware implementation using a Xilinx Virtex 6 FPGA.

Primary author

Jorge Chaves (Cornell University (US))

Presentation materials