The development of a silicon-based L1 tracking trigger system is of utmost importance for CMS for the HL-LHC, in order to maintain physics acceptances for the important trigger objects (such as leptons). A silicon-based L1 tracking trigger has never been realized at this scale and thus it is imperative that its feasibility be demonstrated before the design of the Phase-II Tracker can be finalized. The higher occupancies anticipated at the HL-LHC and the low latencies required at L1 present us with a formidable set of challenges that we need to attack with a well organized R&D campaign. For the off-detector part of tracking trigger, the main challenges are the complex data dispatching and the pattern recognition and track fitting. Data dispatching is where the stubs from many thousands silicon modules must be organized and delivered to the appropriate eta-phi trigger towers. Due to the finite size of the beam’s luminous region in z and the finite curvature of charged particles in the magnetic field, some stubs must be duplicated and sent to multiple towers in an intelligent way. Since all this must be done within a very short time (of the order of a micro-second), communication between processing elements in different towers requires very high bandwidth and very low latency. In addition, extremely fast and effective pattern recognition and track fitting is also required. Extensive R&D and experimentation of innovative ideas is needed in this area. Therefore, it is desirable that the design of the overall architecture can address the need for efficient dispatching of the data for time and regional multiplexing and the capability of providing a common flexible framework to test different possible solutions for track finding and fitting. For this purpose, a custom full mesh enabled ATCA board called Pulsar II has been designed at Fermilab with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth board-to-board communication channels. In addition, pattern recognition mezzanine cards can be designed for Pulsar II, and this will be the pattern recognition engine and can host FPGA with the new associative memory chips being developed. In this talk, we will present a status report of the off-detector L1 silicon-based tracking trigger R&D program, from system level architecture considerations to the concept of a Vertical Slice Demonstration, with board and chip level prototype results designed for such a demonstration. This R&D is being pursued in collaboration with a few CMS institutions, and some of the R&D activities will be presented in other talks at this workshop.
