Speaker
Description
Summary
The presentation will cover details of the CMS data acquisition and trigger upgrade planned for the next run at the LHC, concentrating on the replacement of the Level-1 calorimeter trigger. As the LHC restarts and delivers higher luminosity collisions, exceeding the design parameters, the current CMS trigger system will not be capable of maintaining the high efficiency required for the CMS physics program. The replacement of the trigger system is also a good opportunity to consider even more efficient ways of selecting electrons, photons, tau leptons, reconstructing jets and performing energy sums. In these intense conditions, the implementation of pile-up mitigation techniques is required to reach acceptable performance.
Modern technologies offer an effective solution to achieve these goals. The trigger primitives generated by the detector will be transmitted by newly installed optical link boards (4.5 to 6.4 Gb/s) replacing the existing copper cables (1.2 Gb/s), to a new system based on the microTCA electronics standard. The system is based on custom designed AMC (Advanced Mezzanine Boards) with Xilinx Virtex 7 FPGAs. These boards provide up to 144 high-speed optical serial links, running at speeds up to 10 Gbps allowing to gather information from the entire calorimeter for each event in one FPGA, where sophisticated algorithms may be implemented. The complete view of the calorimeter will allow the trigger to compute global quantities such as the average energy density that can be used to estimate the pile-up level. The resulting increase in rejection power will permit the experiment keep low trigger thresholds on physics objects.
The talk will cover the design of the upgraded system, including hardware, software and firmware. Particular emphasis is placed on the results of prototype testing and the experience gained which is of general application to the design of such systems. For example, design of these advanced algorithms in vhdl, optimized floorplanning, organised dataflow and processing time. The integration of prototype cards into a test system with Ethernet communication, trigger data-flow, timing control and a data-acquisition path, allowing algorithm testing and benchmark results for latency and resource usage, is also presented. Results from integration tests between subcomponents are also included and finally future plans are summarized.
