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Description
Summary
The PixFEL project represents the first stage toward the development of advanced X-ray imaging instrumentation for experiments at the next generation X-ray free electron lasers (X-FELs). The project aims at substantially advancing the state-of-the-art in the field of 2D X-ray imaging detectors by taking advantage of some key technology options. For this purpose, the collaboration is working on the design of the fundamental building blocks and investigating and implementing the enabling technologies for assembling a three-layer (one for the detector and two for the readout chip), four-side buttable chip. The ambitious goal of the research program, in the long term, is the fabrication of an X-ray camera with single photon resolution, 1 to 10$^4$ photons @ 1 keV to 10 keV input dynamic range, 1 kevent in pixel memory, 100 $\mu$m pitch and the capability to be operated at the fast (1 MHz or larger) rates foreseen for the future X-FEL machines. Active edge pixel technology is an interesting solution to reduce the gap between the active area and the edge of the sensor and minimize the dead area in the sensor layer. Process optimization is required for improved quantum efficiency at 10 keV. Also, a careful study of plasma effects and radiation damage is needed for a full assessment of the device operation in the environment of X-FEL experiments. The building blocks of the readout chip are being designed in a 65 nm CMOS technology. The front-end electronics has to cover the wide input dynamic range while preserving single photon resolution at small signals. In the PixFEL project, this is achieved by means of a charge preamplifier with non-linear charge sensitivity, based on the voltage dependent impedance of a MOS capacitor in the feedback network. A time-variant shaper is used to process the signal at the preamplifier output. In-pixel A-to-D conversion is performed with a 10 bit successive approximation register (SAR) ADC, with up to 5 Msample/s sampling rate. The analog chain and the ADC will be located in one layer of the front-end chip. In order to store 1000 events, high density memory cells will be packed in the second layer. A through silicon via (TSV) technology, with a via diameter in the order of a few micrometers, may be exploited to enable inter-layer communication. Lower density, larger diameter TSVs can be used to access the input/output pads of the chip through the substrate of the second layer, in order to avoid wire bonding and carry out side-by-side placement of the elementary tiles. The activity of the project in its present stage is mainly focused on the design of the microelectronic building blocks and on the simulation of the slim edge pixel sensor. Submission of the first test structures is planned for the last quarter of 2014.
