Speaker
Description
Summary
In modern and future detector systems of particle physics experiments, the data serialization and subsequent transmission with highest possible rate and lowest power, is of crucial importance. The serialization and data transmission aspects are currently under study for the luminosity detector at the future linear colliders (ILC/CLIC) and for strip tracker readout in LHCb upgrade experiment. Since the readout architecture of these experiments comprises an ADC in each channel the data serialization from multichannel ADC and a fast power-efficient serial data transmission needs to be implemented. For this an efficient PLL with different clock division factors is required. A multi-phase DLL is needed in various points of readout chain for the precise time alignment (e.g. at ADC sampling instance)
In this work we discuss the development of the key block for clock multiplication and phase alignment i.e. the PLL and DLL. The designs were optimized for low power consumption and usage as general purpose blocks. The simulations show that PLL should work up to 450MHz. A standard second order Phase-Locked Loop architecture was chosen for the PLL design. It contains a Phase and Frequency Detector (PFD), a Charge Pump (CP), a Low Pass Filter (LPF) and a multi-phase Voltage Controlled Oscillator (VCO). The "current starved" inverters were used in the VCO design. The VCO generates 16 independent clock phases, but only two of them ore available at the PLL output (selected via internal multiplexers). Variable clock division factor equal 2, 4, 6 or 8 may be set in the PLL feedback loop making the design more flexible. The PLL has period jitter around 6.7ps (RMS) at typical frequency 160MHz.
The DLL contains a PFD, a CP, a LPF and a Voltage Controlled Delay Line (VCDL). The 64 delay stages were used in the VCDL design, each of which based on two "current starved" inverters. The output clock phase (1 of 64) can be selected by multiplexer with time precision around 390ps for typical input clock 40MHz. The period jitter of the DLL is around 3.2ps - 7.8ps (RMS) and depends on selected output phase (better for firsts VCDL outputs).
The complete circuits were designed, simulated and fabricated in 130nm CMOS technology. The PLL layout occupies 450um x 260um, while the DLL area is little bigger (680um x 210um). The prototype measurements of the PLL were done in the frequency range 30MHz - 450MHz at default 1.2V power supply and showed the proper circuit operation. It was verified that all clock division factors are working properly. For the default 1.2V power supply, division factor equal 4 and typical PLL clock (160MHz) the measured power consumption was about 0.5mW. The DLL preliminary measurements show that the circuit is fully functional in frequency range 18MHz - 62MHz. The power consumption at typical power supply 1.2V and input frequency 40MHz is around 0.7mW. The output clock phase alignment was also positively verified.
