One of the main features of the European XFEL will be high brilliance pulses at a high repetition rate. The pulses will form a bunch train repeating at a frequency of 10 Hz. Each bunch train contains 2700 pulses of >1012 photons of 12keV each, separated by 220 ns.
The key requirements of AGIPD were derived from the unique properties of this source:
- A high dynamic range, extending from single photon sensitivity to 104 photons
- A frame rate of 4.5 MHz
- As many good images as possible
- Radiation hardness of several 10kGy
Before the development of the full-scale ASIC “AGIPD 1.0” 6 MPW prototypes were designed in IBM 0.13µm 8RF-DM technology. Those prototypes were used to prove the adaptive gain concept used to cope with the dynamic range, to measure the characteristics of analogue and digital blocks, and to investigate the radiation hardness of those blocks and the chosen technology.
The full-scale chip is an ~13x14 mm2 ASIC containing a 64x64 array of 200x200 µm2 pixels, steered via digital buffers on two sides by the controlling periphery logic. The third side of the pixel matrix is connected to 4 analogue multiplexers, driven by the logic block as well. The ASIC is supplied with 1.5V and has a consumption of approximately 1.65W in operating mode.
The input stage of each pixel is a charge sensitive preamplifier (CSA), which integrates the charge of the 500µm thick silicon sensor. After the preamplifier the signal path splits into a correlated double sampling (CDS) stage to remove the reset and low frequency noise. The other branch is formed by a discriminator, which, if triggered by an input signal, causes the addition of integration capacitors to the preamplifier feedback. This way the sensitivity is lowered and the dynamic range is increased in two steps. Both, the output of the CDS buffer and a voltage level encoding of the selected gain, are written to an analogue memory capable of storing 352 images. Thus each memory cell is actually composed of two capacitors. Operation of the pixel and the arbitrary addressing of the memory are controlled by the periphery logic. It has a command based serial interface. After each bunch train, the stored signals are read out through the pixel buffer, column buffer and off-chip driver as ‘amplitude’ and ‘gain’ frames.
All prototype ASICs as well as the full scale one were extensively tested and characterized. The non-linearity of the amplitude for all three gain stages was measured to be less than 0.5% and the noise is approximately 260 e- for the highest gain – and always below the Poissonian fluctuation of the input signal. The ASIC features internal DACs to bias the analogue circuits as well as internal calibration structures - a current source and a capacitor based charge injector are used. Experimental results will be presented as well.